Commit 9cc3e4e9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-next-2025-01-07' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next 



UAPI Changes:
- OA new property: 'unblock after N reports' (Ashutosh)

i915 display Changes:
- UHBR rates for Thunderbolt (Kahola)

Driver Changes:
- IRQ related fixes and improvements (Ilia)
 - Revert some changes that break a mesa debug tool (John)
 - Fix migration issues (Nirmoy)
 - Enable GuC's WA_DUAL_QUEUE for newer platforms (Daniele)
 - Move shrink test out of xe_bo (Nirmoy)
 - SRIOV PF: Use correct function to check LMEM provisioning (Michal)
 - Fix a false-positive "Missing outer runtime PM protection" warning (Rodrigo)
 - Make GSCCS disabling message less alarming (Daniele)
 - Fix DG1 power gate sequence (Rodrigo)
 - Xe files fixes (Lucas)
 - Fix a potential TP_printk UAF (Thomas)
 - OA Fixes (Umesh)
 - Fix tlb invalidation when wedging (Lucas)
 - Documentation fix (Lucas)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z31579j3V3XCPFaK@intel.com
parents 0739b8ba 6acea03f

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+35 −4
Original line number Diff line number Diff line
@@ -3070,6 +3070,9 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) 


	val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));



	if (DISPLAY_VER(display) >= 30)

		clock = REG_FIELD_GET(XE3_DDI_CLOCK_SELECT_MASK, val);

	else

		clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);



	drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
@@ -3085,13 +3088,18 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) 
		return 540000;

	case XELPDP_DDI_CLOCK_SELECT_TBT_810:

		return 810000;

	case XELPDP_DDI_CLOCK_SELECT_TBT_312_5:

		return 1000000;

	case XELPDP_DDI_CLOCK_SELECT_TBT_625:

		return 2000000;

	default:

		MISSING_CASE(clock);

		return 162000;

	}

}



static int intel_mtl_tbt_clock_select(int clock)

static int intel_mtl_tbt_clock_select(struct intel_display *display,

				      int clock)

{

	switch (clock) {

	case 162000:
@@ -3102,6 +3110,18 @@ static int intel_mtl_tbt_clock_select(int clock) 
		return XELPDP_DDI_CLOCK_SELECT_TBT_540;

	case 810000:

		return XELPDP_DDI_CLOCK_SELECT_TBT_810;

	case 1000000:

		if (DISPLAY_VER(display) < 30) {

			drm_WARN_ON(display->drm, "UHBR10 not supported for the platform\n");

			return XELPDP_DDI_CLOCK_SELECT_TBT_162;

		}

		return XELPDP_DDI_CLOCK_SELECT_TBT_312_5;

	case 2000000:

		if (DISPLAY_VER(display) < 30) {

			drm_WARN_ON(display->drm, "UHBR20 not supported for the platform\n");

			return XELPDP_DDI_CLOCK_SELECT_TBT_162;

		}

		return XELPDP_DDI_CLOCK_SELECT_TBT_625;

	default:

		MISSING_CASE(clock);

		return XELPDP_DDI_CLOCK_SELECT_TBT_162;
@@ -3114,15 +3134,26 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 
	struct intel_display *display = to_intel_display(encoder);

	enum phy phy = intel_encoder_to_phy(encoder);

	u32 val = 0;

	u32 mask;



	/*

	 * 1. Program PORT_CLOCK_CTL REGISTER to configure

	 * clock muxes, gating and SSC

	 */

	val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));



	if (DISPLAY_VER(display) >= 30) {

		mask = XE3_DDI_CLOCK_SELECT_MASK;

		val |= XE3_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(display, crtc_state->port_clock));

	} else {

		mask = XELPDP_DDI_CLOCK_SELECT_MASK;

		val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(display, crtc_state->port_clock));

	}



	mask |= XELPDP_FORWARD_CLOCK_UNGATE;

	val |= XELPDP_FORWARD_CLOCK_UNGATE;



	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),

		     XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);

		     mask, val);



	/* 2. Read back PORT_CLOCK_CTL REGISTER */

	val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -187,7 +187,9 @@ 
#define   XELPDP_TBT_CLOCK_REQUEST			REG_BIT(19)

#define   XELPDP_TBT_CLOCK_ACK				REG_BIT(18)

#define   XELPDP_DDI_CLOCK_SELECT_MASK			REG_GENMASK(15, 12)

#define   XE3_DDI_CLOCK_SELECT_MASK			REG_GENMASK(16, 12)

#define   XELPDP_DDI_CLOCK_SELECT(val)			REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)

#define   XE3_DDI_CLOCK_SELECT(val)			REG_FIELD_PREP(XE3_DDI_CLOCK_SELECT_MASK, val)

#define   XELPDP_DDI_CLOCK_SELECT_NONE			0x0

#define   XELPDP_DDI_CLOCK_SELECT_MAXPCLK		0x8

#define   XELPDP_DDI_CLOCK_SELECT_DIV18CLK		0x9
@@ -195,6 +197,8 @@ 
#define   XELPDP_DDI_CLOCK_SELECT_TBT_270		0xd

#define   XELPDP_DDI_CLOCK_SELECT_TBT_540		0xe

#define   XELPDP_DDI_CLOCK_SELECT_TBT_810		0xf

#define   XELPDP_DDI_CLOCK_SELECT_TBT_312_5		0x18

#define   XELPDP_DDI_CLOCK_SELECT_TBT_625		0x19

#define   XELPDP_FORWARD_CLOCK_UNGATE			REG_BIT(10)

#define   XELPDP_LANE1_PHY_CLOCK_SELECT			REG_BIT(8)

#define   XELPDP_SSC_ENABLE_PLLA			REG_BIT(1)

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ 
#define RING_IMR(base)				XE_REG((base) + 0xa8)

#define RING_INT_STATUS_RPT_PTR(base)		XE_REG((base) + 0xac)



#define CS_INT_VEC(base)			XE_REG((base) + 0x1b8)



#define RING_EIR(base)				XE_REG((base) + 0xb0)

#define RING_EMR(base)				XE_REG((base) + 0xb4)

#define RING_ESR(base)				XE_REG((base) + 0xb8)
@@ -138,6 +140,7 @@ 


#define RING_MODE(base)				XE_REG((base) + 0x29c)

#define   GFX_DISABLE_LEGACY_MODE		REG_BIT(3)

#define   GFX_MSIX_INTERRUPT_ENABLE		REG_BIT(13)



#define RING_TIMESTAMP(base)			XE_REG((base) + 0x358)

drivers/gpu/drm/xe/regs/xe_lrc_layout.h

+3 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 
#define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)

#define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)



#define CTX_CS_INT_VEC_REG		0x5a

#define CTX_CS_INT_VEC_DATA		(CTX_CS_INT_VEC_REG + 1)



#define INDIRECT_CTX_RING_HEAD		(0x02 + 1)

#define INDIRECT_CTX_RING_TAIL		(0x04 + 1)

#define INDIRECT_CTX_RING_START		(0x06 + 1)

drivers/gpu/drm/xe/tests/xe_bo.c

+14 −2
Original line number Diff line number Diff line
@@ -606,8 +606,6 @@ static void xe_bo_shrink_kunit(struct kunit *test) 
static struct kunit_case xe_bo_tests[] = {

	KUNIT_CASE_PARAM(xe_ccs_migrate_kunit, xe_pci_live_device_gen_param),

	KUNIT_CASE_PARAM(xe_bo_evict_kunit, xe_pci_live_device_gen_param),

	KUNIT_CASE_PARAM_ATTR(xe_bo_shrink_kunit, xe_pci_live_device_gen_param,

			      {.speed = KUNIT_SPEED_SLOW}),

	{}

};
@@ -618,3 +616,17 @@ struct kunit_suite xe_bo_test_suite = { 
	.init = xe_kunit_helper_xe_device_live_test_init,

};

EXPORT_SYMBOL_IF_KUNIT(xe_bo_test_suite);



static struct kunit_case xe_bo_shrink_test[] = {

	KUNIT_CASE_PARAM_ATTR(xe_bo_shrink_kunit, xe_pci_live_device_gen_param,

			      {.speed = KUNIT_SPEED_SLOW}),

	{}

};



VISIBLE_IF_KUNIT

struct kunit_suite xe_bo_shrink_test_suite = {

	.name = "xe_bo_shrink",

	.test_cases = xe_bo_shrink_test,

	.init = xe_kunit_helper_xe_device_live_test_init,

};

EXPORT_SYMBOL_IF_KUNIT(xe_bo_shrink_test_suite);