Commit 9e93147f authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: pass dev_priv explicitly to DSPSURF 



Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSURF register macro.

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fc2d7753aa6e8e25303a111bf4b120da6ce8c458.1716469091.git.jani.nikula@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent a99b1e7f

drivers/gpu/drm/i915/display/i9xx_plane.c

+6 −6
Original line number Diff line number Diff line
@@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, 
	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),

		intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),

				  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

	else

		intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
@@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, 
	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);

		intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0);

	else

		intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);

}
@@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane, 


	intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr);



	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),

	intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),

			  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

}
@@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));

		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;

		base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;

	} else if (DISPLAY_VER(dev_priv) >= 4) {

		if (plane_config->tiling)

			offset = intel_de_read(dev_priv,
@@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
		else

			offset = intel_de_read(dev_priv,

					       DSPLINOFF(dev_priv, i9xx_plane));

		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;

		base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK;

	} else {

		offset = 0;

		base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
@@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, 
		return false;



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);

		intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base);

	else

		intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);

drivers/gpu/drm/i915/display/i9xx_plane_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
#define   DISP_WIDTH(w)			REG_FIELD_PREP(DISP_WIDTH_MASK, (w))



#define _DSPASURF				0x7019C /* i965+ */

#define DSPSURF(plane)				_MMIO_PIPE2(dev_priv, plane, _DSPASURF)

#define DSPSURF(dev_priv, plane)		_MMIO_PIPE2(dev_priv, plane, _DSPASURF)

#define   DISP_ADDR_MASK		REG_GENMASK(31, 12)



#define _DSPATILEOFF				0x701A4 /* i965+ */

drivers/gpu/drm/i915/display/intel_fbc.c

+2 −2
Original line number Diff line number Diff line
@@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc) 
	enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;

	struct drm_i915_private *dev_priv = fbc->i915;



	intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),

			  intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));

	intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane),

			  intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane)));

}



static const struct intel_fbc_funcs i965_fbc_funcs = {

drivers/gpu/drm/i915/gvt/cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -1317,7 +1317,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 
	if (info->plane == PLANE_A) {

		info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);

		info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);

		info->surf_reg = DSPSURF(info->pipe);

		info->surf_reg = DSPSURF(dev_priv, info->pipe);

	} else if (info->plane == PLANE_B) {

		info->ctrl_reg = SPRCTL(info->pipe);

		info->stride_reg = SPRSTRIDE(info->pipe);
@@ -1383,7 +1383,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, 


	info->ctrl_reg = DSPCNTR(dev_priv, info->pipe);

	info->stride_reg = DSPSTRIDE(dev_priv, info->pipe);

	info->surf_reg = DSPSURF(info->pipe);

	info->surf_reg = DSPSURF(dev_priv, info->pipe);



	return 0;

}

drivers/gpu/drm/i915/gvt/fb_decoder.c

+1 −1
Original line number Diff line number Diff line
@@ -251,7 +251,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 


	plane->hw_format = fmt;



	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;

	plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK;

	if (!vgpu_gmadr_is_valid(vgpu, plane->base))

		return  -EINVAL;