Unverified Commit 9eaccb74 authored by Kyrie Wu's avatar Kyrie Wu Committed by AngeloGioacchino Del Regno
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parent 09860910
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+21 −0
Original line number Diff line number Diff line
@@ -1997,6 +1997,27 @@ larb7: smi@17010000 {
			power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
		};

		venc: video-encoder@17020000 {
			compatible = "mediatek,mt8186-vcodec-enc", "mediatek,mt8183-vcodec-enc";
			reg = <0 0x17020000 0 0x2000>;
			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
			iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
				 <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
			clocks = <&vencsys CLK_VENC_CKE1_VENC>;
			clock-names = "venc_sel";
			assigned-clocks = <&topckgen CLK_TOP_VENC>;
			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
			power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
			mediatek,scp = <&scp>;
		};

		camsys: clock-controller@1a000000 {
			compatible = "mediatek,mt8186-camsys";
			reg = <0 0x1a000000 0 0x1000>;