Commit 9ed1a2b8 authored by Sibi Sankar's avatar Sibi Sankar Committed by Bjorn Andersson
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arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region 



Resize the GICR register region as it currently seeps into the CPU Control
Processor mailbox RX region.

Fixes: af16b005 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 87c1870b

arch/arm64/boot/dts/qcom/x1e80100.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -5754,7 +5754,7 @@ apps_smmu: iommu@15000000 { 
		intc: interrupt-controller@17000000 {

			compatible = "arm,gic-v3";

			reg = <0 0x17000000 0 0x10000>,     /* GICD */

			      <0 0x17080000 0 0x480000>;    /* GICR * 12 */

			      <0 0x17080000 0 0x300000>;    /* GICR * 12 */



			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;