Commit a0328b39 authored Jun 04, 2024 by Foryun Ma Committed by Dave Jiang Jul 17, 2024

cxl/core/pci: Move reading of control register to immediately before usage



Relocate the reading of the DVSEC control register to immediately
before usage and avoid unnecessary PCI config access from the read
if DVSEC capability check, hdm_count check, or device validity check
results in failure.

Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20240604032151.655-1-foryun.ma@jaguarmicro.com


Signed-off-by: Dave Jiang <dave.jiang@intel.com>

parent 56478475

drivers/cxl/core/pci.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -338,10 +338,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
		if (rc)
		return rc;

		rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
		if (rc)
		return rc;

		if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
		dev_dbg(dev, "Not MEM Capable\n");
		return -ENXIO;
		@@ -368,6 +364,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
		* disabled, and they will remain moot after the HDM Decoder
		* capability is enabled.
		*/
		rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
		if (rc)
		return rc;

		info->mem_enabled = FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl);
		if (!info->mem_enabled)
		return 0;