Commit a0e2025f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.15-tag1' of... 

Merge tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add thermal (TSU) clock, reset, and power domain on Renesas RZ/G3S
 - Add AI accelerator (DRP-AI) clocks and reset on Renesas RZ/V2L
 - Add Image Signal Processor (ISP, FCPVX, VSPX) clocks on Renesas R-Car V3U
   V4H, and V4M
 - Add Watchdog (WDT), SDHI, Interrupt Controller (ICU), Camera (CRU0)
   and CAN-FD clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g047: Add CANFD clocks and resets
  clk: renesas: r9a09g047: Add CRU0 clocks and resets
  clk: renesas: rzv2h: Update error message
  clk: renesas: rzg2l: Update error message
  clk: renesas: r9a09g047: Add ICU clock/reset
  clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
  clk: renesas: r9a09g047: Add SDHI clocks/resets
  clk: renesas: r8a779h0: Add VSPX clock
  clk: renesas: r8a779h0: Add FCPVX clock
  clk: renesas: r8a08g045: Check the source of the CPU PLL settings
  clk: renesas: r9a09g047: Add WDT clocks and resets
  clk: renesas: r8a779h0: Add ISP core clocks
  clk: renesas: r8a779g0: Add ISP core clocks
  clk: renesas: r8a779a0: Add ISP core clocks
  clk: renesas: r8a779a0: Add FCPVX clocks
  clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
  clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP
  clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation
parents 2014c95a 9b12504e

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+8 −0
Original line number Diff line number Diff line
@@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {

	DEF_MOD("isp0",		 16,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp1",		 17,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp2",		 18,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp3",		 19,	R8A779A0_CLK_S1D1),

	DEF_MOD("avb0",		211,	R8A779A0_CLK_S3D2),

	DEF_MOD("avb1",		212,	R8A779A0_CLK_S3D2),

	DEF_MOD("avb2",		213,	R8A779A0_CLK_S3D2),
@@ -238,6 +242,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { 
	DEF_MOD("vspx1",	1029,	R8A779A0_CLK_S1D1),

	DEF_MOD("vspx2",	1030,	R8A779A0_CLK_S1D1),

	DEF_MOD("vspx3",	1031,	R8A779A0_CLK_S1D1),

	DEF_MOD("fcpvx0",	1100,	R8A779A0_CLK_S1D1),

	DEF_MOD("fcpvx1",	1101,	R8A779A0_CLK_S1D1),

	DEF_MOD("fcpvx2",	1102,	R8A779A0_CLK_S1D1),

	DEF_MOD("fcpvx3",	1103,	R8A779A0_CLK_S1D1),

};



static const unsigned int r8a779a0_crit_mod_clks[] __initconst = {

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+2 −0
Original line number Diff line number Diff line
@@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {

	DEF_MOD("isp0",		 16,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("isp1",		 17,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+3 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = {

	DEF_MOD("isp0",		 16,	R8A779H0_CLK_S0D2_VIO),

	DEF_MOD("avb0:rgmii0",	211,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb1:rgmii1",	212,	R8A779H0_CLK_S0D8_HSC),

	DEF_MOD("avb2:rgmii2",	213,	R8A779H0_CLK_S0D8_HSC),
@@ -238,6 +239,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { 
	DEF_MOD("pfc1",		916,	R8A779H0_CLK_CP),

	DEF_MOD("pfc2",		917,	R8A779H0_CLK_CP),

	DEF_MOD("tsc2:tsc1",	919,	R8A779H0_CLK_CL16M),

	DEF_MOD("vspx0",	1028,	R8A779H0_CLK_S0D1_VIO),

	DEF_MOD("fcpvx0",	1100,	R8A779H0_CLK_S0D1_VIO),

	DEF_MOD("ssiu",		2926,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("ssi",		2927,	R8A779H0_CLK_S0D6_PER),

};

drivers/clk/renesas/r9a07g043-cpg.c

+7 −0
Original line number Diff line number Diff line
@@ -89,7 +89,9 @@ static const struct clk_div_table dtable_1_32[] = { 


/* Mux clock tables */

static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };

#ifdef CONFIG_ARM64

static const char * const sel_pll6_2[]	= { ".pll6_250", ".pll5_250" };

#endif

static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" };



static const u32 mtable_sdhi[] = { 1, 2, 3 };
@@ -137,7 +139,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),

	DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),

	DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),

#ifdef CONFIG_ARM64

	DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),

#endif

#ifdef CONFIG_RISCV

	DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1),

#endif

	DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),

	DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),

	DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi,

drivers/clk/renesas/r9a07g044-cpg.c

+53 −2
Original line number Diff line number Diff line
@@ -94,6 +94,41 @@ static const struct clk_div_table dtable_1_32[] = { 
	{0, 0},

};



#ifdef CONFIG_CLK_R9A07G054

static const struct clk_div_table dtable_4_32[] = {

	{3, 4},

	{4, 5},

	{5, 6},

	{6, 7},

	{7, 8},

	{8, 9},

	{9, 10},

	{10, 11},

	{11, 12},

	{12, 13},

	{13, 14},

	{14, 15},

	{15, 16},

	{16, 17},

	{17, 18},

	{18, 19},

	{19, 20},

	{20, 21},

	{21, 22},

	{22, 23},

	{23, 24},

	{24, 25},

	{25, 26},

	{26, 27},

	{27, 28},

	{28, 29},

	{29, 30},

	{30, 31},

	{31, 32},

	{0, 0},

};

#endif



static const struct clk_div_table dtable_16_128[] = {

	{0, 16},

	{1, 32},
@@ -114,7 +149,7 @@ static const u32 mtable_sdhi[] = { 1, 2, 3 }; 
static const struct {

	struct cpg_core_clk common[56];

#ifdef CONFIG_CLK_R9A07G054

	struct cpg_core_clk drp[0];

	struct cpg_core_clk drp[3];

#endif

} core_clks __initconst = {

	.common = {
@@ -192,6 +227,9 @@ static const struct { 
	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {

		DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5),

		DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2),

		DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32),

	},

#endif

};
@@ -199,7 +237,7 @@ static const struct { 
static const struct {

	struct rzg2l_mod_clk common[79];

#ifdef CONFIG_CLK_R9A07G054

	struct rzg2l_mod_clk drp[0];

	struct rzg2l_mod_clk drp[5];

#endif

} mod_clks = {

	.common = {
@@ -364,6 +402,16 @@ static const struct { 
	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {

		DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK,

					0x5e8, 0),

		DEF_MOD("stpai_aclk",	R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1,

					0x5e8, 1),

		DEF_MOD("stpai_mclk",	R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M,

					0x5e8, 2),

		DEF_MOD("stpai_dclkin",	R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D,

					0x5e8, 3),

		DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A,

					0x5e8, 4),

	},

#endif

};
@@ -430,6 +478,9 @@ static const struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),

	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),

	DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0),

#ifdef CONFIG_CLK_R9A07G054

	DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0),

#endif

};



static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {