Commit a0f9f854 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12 



It's used internally by firmware.  Using it in the driver
could conflict with firmware.

Reviewed-by: default avatarJames Zhu <James.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1605b5be

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+12 −9
Original line number Diff line number Diff line
@@ -56,12 +56,15 @@ 
 * These are nbio v7_4_1 registers mask. Temporarily define these here since

 * nbio v7_4_1 header is incomplete.

 */

#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK	0x00001000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK	0x00001000L /* Don't use.  Firmware uses this bit internally */

#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK	0x00002000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK	0x00004000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK	0x00008000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK	0x00010000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK	0x00020000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK	0x00040000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK	0x00080000L

#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK	0x00100000L



#define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc

#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
@@ -332,14 +335,14 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 
	.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,

	.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,

	.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,

	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,

	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,

	.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,

	.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,

	.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,

	.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,

	.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,

	.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,

	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,

	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,

	.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,

	.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,

	.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,

	.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK,

	.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK,

	.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK,

};



static void nbio_v7_4_init_registers(struct amdgpu_device *adev)