Unverified Commit a13a806d authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Support Andes PMU extension" 

Yu Chien Peter Lin <peterlin@andestech.com> says:

This patch series introduces the Andes PMU extension, which serves the
same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
is assigned to bit 18 in the custom S-mode local interrupt enable and
pending registers (slie/slip), while the interrupt cause is (256 + 18).

* b4-shazam-merge:
  riscv: andes: Support specifying symbolic firmware and hardware raw events
  riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
  dt-bindings: riscv: Add Andes PMU extension description
  perf: RISC-V: Introduce Andes PMU to support perf event sampling
  perf: RISC-V: Eliminate redundant interrupt enable/disable operations
  riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
  dt-bindings: riscv: Add Andes interrupt controller compatible string
  riscv: errata: Rename defines for Andes

Link: https://lore.kernel.org/r/20240222083946.3977135-1-peterlin@andestech.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents b8e00bdf f5102e31

Documentation/devicetree/bindings/riscv/cpus.yaml

+5 −1
Original line number Diff line number Diff line
@@ -106,7 +106,11 @@ properties: 
        const: 1



      compatible:

        const: riscv,cpu-intc

        oneOf:

          - items:

              - const: andestech,cpu-intc

              - const: riscv,cpu-intc

          - const: riscv,cpu-intc



      interrupt-controller: true

Documentation/devicetree/bindings/riscv/extensions.yaml

+7 −0
Original line number Diff line number Diff line
@@ -477,5 +477,12 @@ properties: 
            latency, as ratified in commit 56ed795 ("Update

            riscv-crypto-spec-vector.adoc") of riscv-crypto.



        - const: xandespmu

          description:

            The Andes Technology performance monitor extension for counter overflow

            and privilege mode filtering. For more details, see Counter Related

            Registers in the AX45MP datasheet.

            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf



additionalProperties: true

...

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ cpu0: cpu@0 { 
			riscv,isa-base = "rv64i";

			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",

					       "zicntr", "zicsr", "zifencei",

					       "zihpm";

					       "zihpm", "xandespmu";

			mmu-type = "riscv,sv39";

			i-cache-size = <0x8000>;

			i-cache-line-size = <0x40>;
@@ -39,7 +39,7 @@ cpu0: cpu@0 { 


			cpu0_intc: interrupt-controller {

				#interrupt-cells = <1>;

				compatible = "riscv,cpu-intc";

				compatible = "andestech,cpu-intc", "riscv,cpu-intc";

				interrupt-controller;

			};

		};

arch/riscv/errata/andes/errata.c

+5 −5
Original line number Diff line number Diff line
@@ -18,9 +18,9 @@ 
#include <asm/sbi.h>

#include <asm/vendorid_list.h>



#define ANDESTECH_AX45MP_MARCHID	0x8000000000008a45UL

#define ANDESTECH_AX45MP_MIMPID		0x500UL

#define ANDESTECH_SBI_EXT_ANDES		0x0900031E

#define ANDES_AX45MP_MARCHID		0x8000000000008a45UL

#define ANDES_AX45MP_MIMPID		0x500UL

#define ANDES_SBI_EXT_ANDES		0x0900031E



#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void) 
	 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and

	 * cache is controllable only then CMO will be applied to the platform.

	 */

	ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,

	ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,

			0, 0, 0, 0, 0, 0);



	return ret.error ? 0 : ret.value;
@@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne 


	done = true;



	if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)

	if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)

		return;



	if (!ax45mp_iocp_sw_workaround())

arch/riscv/include/asm/errata_list.h

+2 −11
Original line number Diff line number Diff line
@@ -12,8 +12,8 @@ 
#include <asm/vendorid_list.h>



#ifdef CONFIG_ERRATA_ANDES

#define ERRATA_ANDESTECH_NO_IOCP	0

#define ERRATA_ANDESTECH_NUMBER		1

#define ERRATA_ANDES_NO_IOCP 0

#define ERRATA_ANDES_NUMBER 1

#endif



#ifdef CONFIG_ERRATA_SIFIVE
@@ -112,15 +112,6 @@ asm volatile(ALTERNATIVE( \ 
#define THEAD_C9XX_RV_IRQ_PMU			17

#define THEAD_C9XX_CSR_SCOUNTEROF		0x5c5



#define ALT_SBI_PMU_OVERFLOW(__ovl)					\

asm volatile(ALTERNATIVE(						\

	"csrr %0, " __stringify(CSR_SSCOUNTOVF),			\

	"csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF),		\

		THEAD_VENDOR_ID, ERRATA_THEAD_PMU,			\

		CONFIG_ERRATA_THEAD_PMU)				\

	: "=r" (__ovl) :						\

	: "memory")



#endif /* __ASSEMBLY__ */



#endif