Commit a19d9349 authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher
Browse files

drm/amdgpu: correct gpu clock counter query on cyan skilfish



Cayn skilfish uses SMUIO v11.0.8 offset.

Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Reviewed-by: default avatarAaron Liu <aaron.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: <stable@vger.kernel.org> # v5.15+
parent c4c8955b
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+21 −0
Original line number Diff line number Diff line
@@ -102,6 +102,11 @@
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0

#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
#define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
#define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
@@ -7316,6 +7321,22 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
	uint64_t clock, clock_lo, clock_hi, hi_check;

	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
	case IP_VERSION(10, 1, 3):
	case IP_VERSION(10, 1, 4):
		preempt_disable();
		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
		/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
		 * roughly every 42 seconds.
		 */
		if (hi_check != clock_hi) {
			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
			clock_hi = hi_check;
		}
		preempt_enable();
		clock = clock_lo | (clock_hi << 32ULL);
		break;
	case IP_VERSION(10, 3, 1):
	case IP_VERSION(10, 3, 3):
	case IP_VERSION(10, 3, 7):