Commit a1a19e11 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

KVM: PPC: Book3S HV: CTRL SPR does not require read-modify-write 



Processors that support KVM HV do not require read-modify-write of
the CTRL SPR to set/clear their thread's runlatch. Just write 1 or 0
to it.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Reviewed-by: default avatarFabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211123095231.1036501-18-npiggin@gmail.com
parent b1adcf57

arch/powerpc/kvm/book3s_hv.c

+1 −1
Original line number Diff line number Diff line
@@ -4071,7 +4071,7 @@ static void load_spr_state(struct kvm_vcpu *vcpu) 
	 */



	if (!(vcpu->arch.ctrl & 1))

		mtspr(SPRN_CTRLT, mfspr(SPRN_CTRLF) & ~1);

		mtspr(SPRN_CTRLT, 0);

}



static void store_spr_state(struct kvm_vcpu *vcpu)

arch/powerpc/kvm/book3s_hv_rmhandlers.S

+6 −9
Original line number Diff line number Diff line
@@ -781,12 +781,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) 
	mtspr	SPRN_AMR,r5

	mtspr	SPRN_UAMOR,r6



	/* Restore state of CTRL run bit; assume 1 on entry */

	/* Restore state of CTRL run bit; the host currently has it set to 1 */

	lwz	r5,VCPU_CTRL(r4)

	andi.	r5,r5,1

	bne	4f

	mfspr	r6,SPRN_CTRLF

	clrrdi	r6,r6,1

	li	r6,0

	mtspr	SPRN_CTRLT,r6

4:

	/* Secondary threads wait for primary to have done partition switch */
@@ -1209,12 +1208,12 @@ guest_bypass: 
	stw	r0, VCPU_CPU(r9)

	stw	r0, VCPU_THREAD_CPU(r9)



	/* Save guest CTRL register, set runlatch to 1 */

	/* Save guest CTRL register, set runlatch to 1 if it was clear */

	mfspr	r6,SPRN_CTRLF

	stw	r6,VCPU_CTRL(r9)

	andi.	r0,r6,1

	bne	4f

	ori	r6,r6,1

	li	r6,1

	mtspr	SPRN_CTRLT,r6

4:

	/*
@@ -2184,8 +2183,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_TM) 
	 * Also clear the runlatch bit before napping.

	 */

kvm_do_nap:

	mfspr	r0, SPRN_CTRLF

	clrrdi	r0, r0, 1

	li	r0,0

	mtspr	SPRN_CTRLT, r0



	li	r0,1
@@ -2204,8 +2202,7 @@ kvm_nap_sequence: /* desired LPCR value in r5 */ 


	bl	isa206_idle_insn_mayloss



	mfspr	r0, SPRN_CTRLF

	ori	r0, r0, 1

	li	r0,1

	mtspr	SPRN_CTRLT, r0



	mtspr	SPRN_SRR1, r3