Commit a29997b7 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Limit VTotal range to max hw cap minus fp 



[WHY & HOW]
Hardware does not support the VTotal to be between fp2 lines of the
maximum possible VTotal, so add a capability flag to track it and apply
where necessary.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Reviewed-by: default avatarAnthony Koo <anthony.koo@amd.com>
Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 24d3749c

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -290,6 +290,7 @@ struct dc_caps { 
	uint16_t subvp_vertical_int_margin_us;

	bool seamless_odm;

	uint32_t max_v_total;

	bool vtotal_limited_by_fp2;

	uint32_t max_disp_clock_khz_at_vmin;

	uint8_t subvp_drr_vblank_start_margin_us;

	bool cursor_not_scaled;

drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c

+25 −2
Original line number Diff line number Diff line
@@ -339,11 +339,22 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in 
	// }

}



static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream)

{

	unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total;



	if (stream->ctx->dc->caps.vtotal_limited_by_fp2) {

		max_hw_v_total -= stream->timing.v_front_porch + 1;

	}



	return max_hw_v_total;

}



static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing,

		struct dc_stream_state *stream,

		struct dml2_context *dml_ctx)

{

	unsigned int hblank_start, vblank_start;

	unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz;



	timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;

	timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
@@ -371,11 +382,23 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf 
		- stream->timing.v_border_top - stream->timing.v_border_bottom;



	timing->drr_config.enabled = stream->ignore_msa_timing_param;

	timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz;

	timing->drr_config.drr_active_variable = stream->vrr_active_variable;

	timing->drr_config.drr_active_fixed = stream->vrr_active_fixed;

	timing->drr_config.disallowed = !stream->allow_freesync;



	/* limit min refresh rate to DC cap */

	min_hardware_refresh_in_uhz = stream->timing.min_refresh_in_uhz;

	if (stream->ctx->dc->caps.max_v_total != 0) {

		min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),

				(stream->timing.h_total * (long long)calc_max_hardware_v_total(stream)));

	}



	if (stream->timing.min_refresh_in_uhz > min_hardware_refresh_in_uhz) {

		timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz;

	} else {

		timing->drr_config.min_refresh_uhz = min_hardware_refresh_in_uhz;

	}



	if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase &&

			stream->ctx->dc->config.enable_fpo_flicker_detection == 1)

		timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -2353,6 +2353,7 @@ static bool dcn30_resource_construct( 


	dc->caps.dp_hdmi21_pcon_support = true;

	dc->caps.max_v_total = (1 << 15) - 1;

	dc->caps.vtotal_limited_by_fp2 = true;



	/* read VBIOS LTTPR caps */

	{

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1233,6 +1233,7 @@ static bool dcn302_resource_construct( 
	dc->caps.extended_aux_timeout_support = true;

	dc->caps.dmcub_support = true;

	dc->caps.max_v_total = (1 << 15) - 1;

	dc->caps.vtotal_limited_by_fp2 = true;



	/* Color pipeline capabilities */

	dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

+1 −0
Original line number Diff line number Diff line
@@ -1178,6 +1178,7 @@ static bool dcn303_resource_construct( 
	dc->caps.extended_aux_timeout_support = true;

	dc->caps.dmcub_support = true;

	dc->caps.max_v_total = (1 << 15) - 1;

	dc->caps.vtotal_limited_by_fp2 = true;



	/* Color pipeline capabilities */

	dc->caps.color.dpp.dcn_arch = 1;