Commit a2a2a69d authored by Jason Gunthorpe's avatar Jason Gunthorpe
Browse files

Merge tag 'v5.15' into rdma.git for-next



Pull in the accepted for-rc patches as the next merge needs a newer base.

Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parents 9ed8110c 8bb7eca9
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+2 −0
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ Al Viro <viro@zenIV.linux.org.uk>
Andi Kleen <ak@linux.intel.com> <ak@suse.de>
Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
Andreas Herrmann <aherrman@de.ibm.com>
Andrej Shadura <andrew.shadura@collabora.co.uk>
Andrej Shadura <andrew@shadura.me> <andrew@beldisplaytech.com>
Andrew Morton <akpm@linux-foundation.org>
Andrew Murray <amurray@thegoodpenguin.co.uk> <amurray@embedded-bits.co.uk>
Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>
+6 −5
Original line number Diff line number Diff line
@@ -32,13 +32,13 @@ properties:
  "#size-cells":
    const: 1

  pinctrl:
    $ref: ../pinctrl/brcm,ns-pinmux.yaml

patternProperties:
  '^clock-controller@[a-f0-9]+$':
    $ref: ../clock/brcm,iproc-clocks.yaml

  '^pin-controller@[a-f0-9]+$':
    $ref: ../pinctrl/brcm,ns-pinmux.yaml

  '^thermal@[a-f0-9]+$':
    $ref: ../thermal/brcm,ns-thermal.yaml

@@ -73,9 +73,10 @@ examples:
                                 "iprocfast", "sata1", "sata2";
        };

        pinctrl {
        pin-controller@1c0 {
            compatible = "brcm,bcm4708-pinmux";
            offset = <0x1c0>;
            reg = <0x1c0 0x24>;
            reg-names = "cru_gpio_control";
        };

        thermal@2c0 {
+14 −19
Original line number Diff line number Diff line
@@ -17,9 +17,6 @@ description:

  A list of pins varies across chipsets so few bindings are available.

  Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
  node.

properties:
  compatible:
    enum:
@@ -27,10 +24,11 @@ properties:
      - brcm,bcm4709-pinmux
      - brcm,bcm53012-pinmux

  offset:
    description: offset of pin registers in the CRU block
  reg:
    maxItems: 1
    $ref: /schemas/types.yaml#/definitions/uint32-array

  reg-names:
    const: cru_gpio_control

patternProperties:
  '-pins$':
@@ -72,23 +70,20 @@ allOf:
                        uart1_grp ]

required:
  - offset
  - reg
  - reg-names

additionalProperties: false

examples:
  - |
    cru@1800c100 {
        compatible = "syscon", "simple-mfd";
        reg = <0x1800c100 0x1a4>;

        pinctrl {
    pin-controller@1800c1c0 {
        compatible = "brcm,bcm4708-pinmux";
            offset = <0xc0>;
        reg = <0x1800c1c0 0x24>;
        reg-names = "cru_gpio_control";

        spi-pins {
            function = "spi";
            groups = "spi_grp";
        };
    };
    };
+5 −4
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@@ -30,10 +30,11 @@ The ``ice`` driver reports the following versions
        PHY, link, etc.
    * - ``fw.mgmt.api``
      - running
      - 1.5
      - 2-digit version number of the API exported over the AdminQ by the
        management firmware. Used by the driver to identify what commands
        are supported.
      - 1.5.1
      - 3-digit version number (major.minor.patch) of the API exported over
        the AdminQ by the management firmware. Used by the driver to
        identify what commands are supported. Historical versions of the
        kernel only displayed a 2-digit version number (major.minor).
    * - ``fw.mgmt.build``
      - running
      - 0x305d955f
+5 −5
Original line number Diff line number Diff line
@@ -59,8 +59,8 @@ specified with a ``sockaddr`` type, with a single-byte endpoint address:
    };

    struct sockaddr_mctp {
            unsigned short int	smctp_family;
            int			smctp_network;
            __kernel_sa_family_t smctp_family;
            unsigned int         smctp_network;
            struct mctp_addr     smctp_addr;
            __u8                 smctp_type;
            __u8                 smctp_tag;
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