Commit a313d905 authored by Nitin Gote's avatar Nitin Gote Committed by Lucas De Marchi
Browse files

drm/xe: Rename MCFG_MCR_SELECTOR to STEER_SEMAPHORE 



The register at offset 0xfd0 was incorrectly named MCFG_MCR_SELECTOR,
likely copied from i915. According to the hardware specification (Bspec),
this register is actually called STEER_SEMAPHORE.

Rename the register definition and update its usage in xe_gt_mcr.c to
match the official hardware documentation.

No functional changes.

v2: Add Bspec reference (Tejas)

Bspec: 67113
Signed-off-by: default avatarNitin Gote <nitin.r.gote@intel.com>
Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://lore.kernel.org/r/20250723141039.3848390-1-nitin.r.gote@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent 159afd92

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)

#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)



#define MCFG_MCR_SELECTOR			XE_REG(0xfd0)

#define STEER_SEMAPHORE				XE_REG(0xfd0)

#define MTL_MCR_SELECTOR			XE_REG(0xfd4)

#define SF_MCR_SELECTOR				XE_REG(0xfd8)

#define MCR_SELECTOR				XE_REG(0xfdc)

drivers/gpu/drm/xe/xe_gt_mcr.c

+1 −3
Original line number Diff line number Diff line
@@ -46,8 +46,6 @@ 
 * MCR registers are not available on Virtual Function (VF).

 */



#define STEER_SEMAPHORE		XE_REG(0xFD0)



static inline struct xe_reg to_xe_reg(struct xe_reg_mcr reg_mcr)

{

	return reg_mcr.__reg;
@@ -533,7 +531,7 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt) 
		u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |

			REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);



		xe_mmio_write32(&gt->mmio, MCFG_MCR_SELECTOR, steer_val);

		xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, steer_val);

		xe_mmio_write32(&gt->mmio, SF_MCR_SELECTOR, steer_val);

		/*

		 * For GAM registers, all reads should be directed to instance 1