Commit a38b1061 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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riscv: dts: renesas: r9a07g043f: Add L2 cache node 



Add L2 cache node for RZ/Five SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 587c848a

arch/riscv/boot/dts/renesas/r9a07g043f.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ cpu0: cpu@0 { 
			i-cache-line-size = <0x40>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <0x40>;

			next-level-cache = <&l2cache>;

			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;

			operating-points-v2 = <&cluster0_opp>;
@@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 { 
		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;

		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;

	};



	l2cache: cache-controller@13400000 {

		compatible = "andestech,ax45mp-cache", "cache";

		reg = <0x0 0x13400000 0x0 0x100000>;

		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;

		cache-size = <0x40000>;

		cache-line-size = <64>;

		cache-sets = <1024>;

		cache-unified;

		cache-level = <2>;

	};

};