Commit a3a74f9b authored by Michael Walle's avatar Michael Walle Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-j722s-main: fix the audio refclk source 



At the moment the clock parent of the audio extclk output is PLL1_HSDIV6
of the main domain. This very clock output is also used among various IP
cores, for example for the USB1 LPM clock. The audio extclock being an
external clock output with a variable frequency, it is likely that a
user of this clock will try to set it's frequency to a different value,
i.e. an audio codec. Because that clock output is used also for other IP
cores, bad things will happen.

Instead of using PLL1_HSDIV6 use the PLL2_HSDIV8 as a sane default, as
this output is exclusively used among other audio peripherals.

Signed-off-by: default avatarMichael Walle <mwalle@kernel.org>
Link: https://patch.msgid.link/20251017102228.530517-2-mwalle@kernel.org


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent b2f45bdc

arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -443,7 +443,7 @@ audio_refclk0: clock@82e0 { 
		reg = <0x82e0 0x4>;

		clocks = <&k3_clks 157 0>;

		assigned-clocks = <&k3_clks 157 0>;

		assigned-clock-parents = <&k3_clks 157 15>;

		assigned-clock-parents = <&k3_clks 157 16>;

		#clock-cells = <0>;

	};
@@ -452,7 +452,7 @@ audio_refclk1: clock@82e4 { 
		reg = <0x82e4 0x4>;

		clocks = <&k3_clks 157 18>;

		assigned-clocks = <&k3_clks 157 18>;

		assigned-clock-parents = <&k3_clks 157 33>;

		assigned-clock-parents = <&k3_clks 157 34>;

		#clock-cells = <0>;

	};

};