Commit a409901f authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Rodrigo Vivi
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drm/xe/xe2: Add workaround 14020013138 



This workaround applies to Xe2_LPG A0

V3:
  - Apply rule RENDER class
V2(Matt):
  - Apply WA in lrc context

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent f91bacce

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -93,6 +93,9 @@ 
#define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)

#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)



#define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)

#define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)



#define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)

#define   TBIMR_FAST_CLIP			REG_BIT(5)

drivers/gpu/drm/xe/xe_wa.c

+5 −0
Original line number Diff line number Diff line
@@ -714,6 +714,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))

	},

	{ XE_RTP_NAME("14020013138"),

	  XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),

		       ENGINE_CLASS(RENDER)),

	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))

	},



	{}

};