Commit a4937e97 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom: document the Milos Video Clock Controller



Add bindings documentation for the Milos (e.g. SM7635) Video Clock
Controller.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 980d7c84
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,milos-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Video Clock & Reset Controller on Milos

maintainers:
  - Luca Weiss <luca.weiss@fairphone.com>

description: |
  Qualcomm video clock control module provides the clocks, resets and power
  domains on Milos.

  See also: include/dt-bindings/clock/qcom,milos-videocc.h

properties:
  compatible:
    const: qcom,milos-videocc

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Sleep clock source
      - description: Video AHB clock from GCC

required:
  - compatible
  - clocks

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,milos-gcc.h>
    clock-controller@aaf0000 {
        compatible = "qcom,milos-videocc";
        reg = <0x0aaf0000 0x10000>;
        clocks = <&bi_tcxo_div2>,
                 <&bi_tcxo_ao_div2>,
                 <&sleep_clk>,
                 <&gcc GCC_VIDEO_AHB_CLK>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        #power-domain-cells = <1>;
    };

...
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
 */

#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H

/* VIDEO_CC clocks */
#define VIDEO_CC_PLL0						0
#define VIDEO_CC_AHB_CLK					1
#define VIDEO_CC_AHB_CLK_SRC					2
#define VIDEO_CC_MVS0_CLK					3
#define VIDEO_CC_MVS0_CLK_SRC					4
#define VIDEO_CC_MVS0_DIV_CLK_SRC				5
#define VIDEO_CC_MVS0_SHIFT_CLK					6
#define VIDEO_CC_MVS0C_CLK					7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				8
#define VIDEO_CC_MVS0C_SHIFT_CLK				9
#define VIDEO_CC_SLEEP_CLK					10
#define VIDEO_CC_SLEEP_CLK_SRC					11
#define VIDEO_CC_XO_CLK						12
#define VIDEO_CC_XO_CLK_SRC					13

/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR					0
#define VIDEO_CC_MVS0_BCR					1
#define VIDEO_CC_MVS0C_CLK_ARES					2
#define VIDEO_CC_MVS0C_BCR					3

/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC					0
#define VIDEO_CC_MVS0C_GDSC					1

#endif