Commit a4cb5ece authored by Xin Li's avatar Xin Li Committed by Thomas Gleixner
Browse files

x86/cpufeatures,opcode,msr: Add the WRMSRNS instruction support 



WRMSRNS is an instruction that behaves exactly like WRMSR, with
the only difference being that it is not a serializing instruction
by default. Under certain conditions, WRMSRNS may replace WRMSR to
improve performance.

Add its CPU feature bit, opcode to the x86 opcode map, and an
always inline API __wrmsrns() to embed WRMSRNS into the code.

Signed-off-by: default avatarXin Li <xin3.li@intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Tested-by: default avatarShan Kang <shan.kang@intel.com>
Acked-by: default avatarMasami Hiramatsu (Google) <mhiramat@kernel.org>
Acked-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20231205105030.8698-2-xin3.li@intel.com
parent 6613476e

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -327,6 +327,7 @@ 
#define X86_FEATURE_FSRS		(12*32+11) /* "" Fast short REP STOSB */

#define X86_FEATURE_FSRC		(12*32+12) /* "" Fast short REP {CMPSB,SCASB} */

#define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */

#define X86_FEATURE_WRMSRNS		(12*32+19) /* "" Non-serializing WRMSR */

#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */

#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */

#define X86_FEATURE_LAM			(12*32+26) /* Linear Address Masking */

arch/x86/include/asm/msr.h

+18 −0
Original line number Diff line number Diff line
@@ -97,6 +97,19 @@ static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high) 
		     : : "c" (msr), "a"(low), "d" (high) : "memory");

}



/*

 * WRMSRNS behaves exactly like WRMSR with the only difference being

 * that it is not a serializing instruction by default.

 */

static __always_inline void __wrmsrns(u32 msr, u32 low, u32 high)

{

	/* Instruction opcode for WRMSRNS; supported in binutils >= 2.40. */

	asm volatile("1: .byte 0x0f,0x01,0xc6\n"

		     "2:\n"

		     _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR)

		     : : "c" (msr), "a"(low), "d" (high));

}



#define native_rdmsr(msr, val1, val2)			\

do {							\

	u64 __val = __rdmsr((msr));			\
@@ -297,6 +310,11 @@ do { \ 


#endif	/* !CONFIG_PARAVIRT_XXL */



static __always_inline void wrmsrns(u32 msr, u64 val)

{

	__wrmsrns(msr, val, val >> 32);

}



/*

 * 64-bit version of wrmsr_safe():

 */

arch/x86/lib/x86-opcode-map.txt

+1 −1
Original line number Diff line number Diff line
@@ -1051,7 +1051,7 @@ GrpTable: Grp6 
EndTable



GrpTable: Grp7

0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)

0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) | WRMSRNS (110),(11B)

1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)

2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)

3: LIDT Ms

tools/arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -322,6 +322,7 @@ 
#define X86_FEATURE_FSRS		(12*32+11) /* "" Fast short REP STOSB */

#define X86_FEATURE_FSRC		(12*32+12) /* "" Fast short REP {CMPSB,SCASB} */

#define X86_FEATURE_LKGS		(12*32+18) /* "" Load "kernel" (userspace) GS */

#define X86_FEATURE_WRMSRNS		(12*32+19) /* "" Non-serializing WRMSR */

#define X86_FEATURE_AMX_FP16		(12*32+21) /* "" AMX fp16 Support */

#define X86_FEATURE_AVX_IFMA            (12*32+23) /* "" Support for VPMADD52[H,L]UQ */

#define X86_FEATURE_LAM			(12*32+26) /* Linear Address Masking */

tools/arch/x86/lib/x86-opcode-map.txt

+1 −1
Original line number Diff line number Diff line
@@ -1051,7 +1051,7 @@ GrpTable: Grp6 
EndTable



GrpTable: Grp7

0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B)

0: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B) | PCONFIG (101),(11B) | ENCLV (000),(11B) | WRMSRNS (110),(11B)

1: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B) | ENCLS (111),(11B)

2: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B) | ENCLU (111),(11B)

3: LIDT Ms