Commit a507e750 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.11-2024-08-08' of... 

Merge tag 'amd-drm-fixes-6.11-2024-08-08' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.11-2024-08-08:

amdgpu:
- DMCUB fix
- Fix DET programming on some DCNs
- DCC fixes
- DCN 4.0.1 fixes
- SMU 14.0.x update
- MMHUB fix
- DCN 3.1.4 fix
- GC 12.0 fixes
- Fix soft recovery error propogation
- SDMA 7.0 fixes
- DSC fix

drm buddy:
- Add start address to trim function

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240808161134.1227671-1-alexander.deucher@amd.com
parents 062fd0a6 6ad9dafb

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+6 −0
Original line number Diff line number Diff line
@@ -156,6 +156,8 @@ struct amdgpu_gmc_funcs { 
				      uint64_t addr, uint64_t *flags);

	/* get the amount of memory used by the vbios for pre-OS console */

	unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);

	/* get the DCC buffer alignment */

	unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev);



	enum amdgpu_memory_partition (*query_mem_partition_mode)(

		struct amdgpu_device *adev);
@@ -363,6 +365,10 @@ struct amdgpu_gmc { 
	(adev)->gmc.gmc_funcs->override_vm_pte_flags			\

		((adev), (vm), (addr), (pte_flags))

#define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev))

#define amdgpu_gmc_get_dcc_alignment(adev) ({			\

	typeof(adev) _adev = (adev);				\

	_adev->gmc.gmc_funcs->get_dcc_alignment(_adev);		\

})



/**

 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+1 −2
Original line number Diff line number Diff line
@@ -264,9 +264,8 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job, 
	struct dma_fence *fence = NULL;

	int r;



	/* Ignore soft recovered fences here */

	r = drm_sched_entity_error(s_entity);

	if (r && r != -ENODATA)

	if (r)

		goto error;



	if (!fence && job->gang_submit)

drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

+34 −2
Original line number Diff line number Diff line
@@ -456,6 +456,7 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, 
	u64 vis_usage = 0, max_bytes, min_block_size;

	struct amdgpu_vram_mgr_resource *vres;

	u64 size, remaining_size, lpfn, fpfn;

	unsigned int adjust_dcc_size = 0;

	struct drm_buddy *mm = &mgr->mm;

	struct drm_buddy_block *block;

	unsigned long pages_per_block;
@@ -511,7 +512,19 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, 
		/* Allocate blocks in desired range */

		vres->flags |= DRM_BUDDY_RANGE_ALLOCATION;



	if (bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC &&

	    adev->gmc.gmc_funcs->get_dcc_alignment)

		adjust_dcc_size = amdgpu_gmc_get_dcc_alignment(adev);



	remaining_size = (u64)vres->base.size;

	if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) {

		unsigned int dcc_size;



		dcc_size = roundup_pow_of_two(vres->base.size + adjust_dcc_size);

		remaining_size = (u64)dcc_size;



		vres->flags |= DRM_BUDDY_TRIM_DISABLE;

	}



	mutex_lock(&mgr->lock);

	while (remaining_size) {
@@ -521,7 +534,10 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, 
			min_block_size = mgr->default_page_size;



		size = remaining_size;

		if ((size >= (u64)pages_per_block << PAGE_SHIFT) &&



		if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size)

			min_block_size = size;

		else if ((size >= (u64)pages_per_block << PAGE_SHIFT) &&

			 !(size & (((u64)pages_per_block << PAGE_SHIFT) - 1)))

			min_block_size = (u64)pages_per_block << PAGE_SHIFT;
@@ -553,6 +569,22 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, 
	}

	mutex_unlock(&mgr->lock);



	if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && adjust_dcc_size) {

		struct drm_buddy_block *dcc_block;

		unsigned long dcc_start;

		u64 trim_start;



		dcc_block = amdgpu_vram_mgr_first_block(&vres->blocks);

		/* Adjust the start address for DCC buffers only */

		dcc_start =

			roundup((unsigned long)amdgpu_vram_mgr_block_start(dcc_block),

				adjust_dcc_size);

		trim_start = (u64)dcc_start;

		drm_buddy_block_trim(mm, &trim_start,

				     (u64)vres->base.size,

				     &vres->blocks);

	}



	vres->base.start = 0;

	size = max_t(u64, amdgpu_vram_mgr_blocks_size(&vres->blocks),

		     vres->base.size);

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+27 −0
Original line number Diff line number Diff line
@@ -202,6 +202,12 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)

};



static const struct soc15_reg_golden golden_settings_gc_12_0[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),

	SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)

};



#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3432,6 +3438,24 @@ static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 
	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);

}



static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)

{

	if (amdgpu_sriov_vf(adev))

		return;



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(12, 0, 0):

	case IP_VERSION(12, 0, 1):

		if (adev->rev_id == 0)

			soc15_program_register_sequence(adev,

					golden_settings_gc_12_0,

					(const u32)ARRAY_SIZE(golden_settings_gc_12_0));

		break;

	default:

		break;

	}

}



static int gfx_v12_0_hw_init(void *handle)

{

	int r;
@@ -3472,6 +3496,9 @@ static int gfx_v12_0_hw_init(void *handle) 
		}

	}



	if (!amdgpu_emu_mode)

		gfx_v12_0_init_golden_registers(adev);



	adev->gfx.is_poweron = true;



	if (get_gb_addr_config(adev))

drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c

+18 −0
Original line number Diff line number Diff line
@@ -542,6 +542,23 @@ static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 
	return 0;

}



static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev)

{

	unsigned int max_tex_channel_caches, alignment;



	if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) &&

	    amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1))

		return 0;



	max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches;

	if (is_power_of_2(max_tex_channel_caches))

		alignment = (unsigned int)(max_tex_channel_caches / SZ_4);

	else

		alignment = roundup_pow_of_two(max_tex_channel_caches);



	return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K);

}



static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = {

	.flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb,

	.flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid,
@@ -551,6 +568,7 @@ static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 
	.get_vm_pde = gmc_v12_0_get_vm_pde,

	.get_vm_pte = gmc_v12_0_get_vm_pte,

	.get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size,

	.get_dcc_alignment = gmc_v12_0_get_dcc_alignment,

};



static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev)