Unverified Commit a5a15e07 authored by Cyan Yang's avatar Cyan Yang Committed by Palmer Dabbelt
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dt-bindings: riscv: Add xsfvfnrclipxfqf ISA extension description 



Add "xsfvfnrclipxfqf" ISA extension which is provided by SiFive for
FP32-to-int8 ranged clip instructions support.

Signed-off-by: default avatarCyan Yang <cyan.yang@sifive.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250418053239.4351-6-cyan.yang@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 1a6274f0

Documentation/devicetree/bindings/riscv/extensions.yaml

+6 −0
Original line number Diff line number Diff line
@@ -675,6 +675,12 @@ properties: 
            See more details in

            https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification



        - const: xsfvfnrclipxfqf

          description:

            SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification.

            See more details in

            https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions



        # T-HEAD

        - const: xtheadvector

          description: