Unverified Commit a5ea53da authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
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riscv: hwprobe: Add thead vendor extension probing



Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0" which
allows userspace to probe for the new RISCV_ISA_VENDOR_EXT_XTHEADVECTOR
vendor extension.

This new key will allow userspace code to probe for which thead vendor
extensions are supported. This API is modeled to be consistent with
RISCV_HWPROBE_KEY_IMA_EXT_0. The bitmask returned will have each bit
corresponding to a supported thead vendor extension of the cpumask set.
Just like RISCV_HWPROBE_KEY_IMA_EXT_0, this allows a userspace program
to determine all of the supported thead vendor extensions in one call.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarEvan Green <evan@rivosinc.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-10-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent d863910e
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+3 −2
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright 2023 Rivos, Inc
 * Copyright 2023-2024 Rivos, Inc
 */

#ifndef _ASM_HWPROBE_H
@@ -8,7 +8,7 @@

#include <uapi/asm/hwprobe.h>

#define RISCV_HWPROBE_MAX_KEY 10
#define RISCV_HWPROBE_MAX_KEY 11

static inline bool riscv_hwprobe_key_is_valid(__s64 key)
{
@@ -21,6 +21,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
	case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
	case RISCV_HWPROBE_KEY_IMA_EXT_0:
	case RISCV_HWPROBE_KEY_CPUPERF_0:
	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
		return true;
	}

+19 −0
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H
#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H

#include <linux/cpumask.h>

#include <uapi/asm/hwprobe.h>

#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
#else
static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair,
						  const struct cpumask *cpus)
{
	pair->value = 0;
}
#endif

#endif
+37 −0
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/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2024 Rivos, Inc
 */

#ifndef _ASM_RISCV_SYS_HWPROBE_H
#define _ASM_RISCV_SYS_HWPROBE_H

#include <asm/cpufeature.h>

#define VENDOR_EXT_KEY(ext)								\
	do {										\
		if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \
			pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext;			\
		else									\
			missing |= RISCV_HWPROBE_VENDOR_EXT_##ext;			\
	} while (false)

/*
 * Loop through and record extensions that 1) anyone has, and 2) anyone
 * doesn't have.
 *
 * _extension_checks is an arbitrary C block to set the values of pair->value
 * and missing. It should be filled with VENDOR_EXT_KEY expressions.
 */
#define VENDOR_EXTENSION_SUPPORTED(pair, cpus, per_hart_vendor_bitmap, _extension_checks)	\
	do {											\
		int cpu;									\
		u64 missing = 0;								\
		for_each_cpu(cpu, (cpus)) {							\
			struct riscv_isavendorinfo *isainfo = &(per_hart_vendor_bitmap)[cpu];	\
			_extension_checks							\
		}										\
		(pair)->value &= ~missing;							\
	} while (false)										\

#endif /* _ASM_RISCV_SYS_HWPROBE_H */
+2 −1
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright 2023 Rivos, Inc
 * Copyright 2023-2024 Rivos, Inc
 */

#ifndef _UAPI_ASM_HWPROBE_H
@@ -94,6 +94,7 @@ struct riscv_hwprobe {
#define		RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW		2
#define		RISCV_HWPROBE_MISALIGNED_VECTOR_FAST		3
#define		RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED	4
#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0	11
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */

/* Flags */
+3 −0
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */

#define		RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR	(1 << 0)
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