Unverified Commit a5f947c7 authored by Guo Ren's avatar Guo Ren Committed by Palmer Dabbelt
Browse files

riscv: Add ARCH_HAS_PREFETCH[W] support with Zicbop 



Enable Linux prefetch and prefetchw primitives using Zicbop.

Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
Signed-off-by: default avatarGuo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20231231082955.16516-3-guoren@kernel.org


Tested-by: default avatarAndrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20250421142441.395849-4-alexghiti@rivosinc.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
parent 8d496b5a

arch/riscv/include/asm/processor.h

+24 −0
Original line number Diff line number Diff line
@@ -13,6 +13,9 @@ 
#include <vdso/processor.h>



#include <asm/ptrace.h>

#include <asm/insn-def.h>

#include <asm/alternative-macros.h>

#include <asm/hwcap.h>



#define arch_get_mmap_end(addr, len, flags)			\

({								\
@@ -135,6 +138,27 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, 
#define KSTK_EIP(tsk)		(task_pt_regs(tsk)->epc)

#define KSTK_ESP(tsk)		(task_pt_regs(tsk)->sp)



#define PREFETCH_ASM(x)							\

	ALTERNATIVE(__nops(1), PREFETCH_R(x, 0), 0,			\

		    RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)



#define PREFETCHW_ASM(x)						\

	ALTERNATIVE(__nops(1), PREFETCH_W(x, 0), 0,			\

		    RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)



#ifdef CONFIG_RISCV_ISA_ZICBOP

#define ARCH_HAS_PREFETCH

static inline void prefetch(const void *x)

{

	__asm__ __volatile__(PREFETCH_ASM(%0) : : "r" (x) : "memory");

}



#define ARCH_HAS_PREFETCHW

static inline void prefetchw(const void *x)

{

	__asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory");

}

#endif /* CONFIG_RISCV_ISA_ZICBOP */



/* Do necessary setup to start up a newly executed thread. */

extern void start_thread(struct pt_regs *regs,