Commit a669b813 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Enable pipeDMC fault interrupts on tgl+ 



PipeDMC has its own fault interrupt. Enable that so that
we can know if things are failing.

While at it, define the other pipeDMC interrupt as well, even
though we're not currently using it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240605111832.21373-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent ba30cd24

drivers/gpu/drm/i915/display/intel_display_irq.c

+13 −2
Original line number Diff line number Diff line
@@ -837,13 +837,24 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv) 
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)

{

	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))

		return GEN9_PIPE_CURSOR_FAULT |

		return GEN12_PIPEDMC_FAULT |

			GEN9_PIPE_CURSOR_FAULT |

			GEN11_PIPE_PLANE5_FAULT |

			GEN9_PIPE_PLANE4_FAULT |

			GEN9_PIPE_PLANE3_FAULT |

			GEN9_PIPE_PLANE2_FAULT |

			GEN9_PIPE_PLANE1_FAULT;

	else if (DISPLAY_VER(dev_priv) == 12)

		return GEN12_PIPEDMC_FAULT |

			GEN9_PIPE_CURSOR_FAULT |

			GEN11_PIPE_PLANE7_FAULT |

			GEN11_PIPE_PLANE6_FAULT |

			GEN11_PIPE_PLANE5_FAULT |

			GEN9_PIPE_PLANE4_FAULT |

			GEN9_PIPE_PLANE3_FAULT |

			GEN9_PIPE_PLANE2_FAULT |

			GEN9_PIPE_PLANE1_FAULT;

	else if (DISPLAY_VER(dev_priv) >= 11)

	else if (DISPLAY_VER(dev_priv) == 11)

		return GEN9_PIPE_CURSOR_FAULT |

			GEN11_PIPE_PLANE7_FAULT |

			GEN11_PIPE_PLANE6_FAULT |

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -2502,6 +2502,8 @@ 
#define  GEN8_PIPE_FIFO_UNDERRUN	REG_BIT(31)

#define  GEN8_PIPE_CDCLK_CRC_ERROR	REG_BIT(29)

#define  GEN8_PIPE_CDCLK_CRC_DONE	REG_BIT(28)

#define  GEN12_PIPEDMC_INTERRUPT	REG_BIT(26) /* tgl+ */

#define  GEN12_PIPEDMC_FAULT		REG_BIT(25) /* tgl+ */

#define  XELPD_PIPE_SOFT_UNDERRUN	REG_BIT(22) /* adl/dg2+ */

#define  GEN11_PIPE_PLANE7_FAULT	REG_BIT(22) /* icl/tgl */

#define  XELPD_PIPE_HARD_UNDERRUN	REG_BIT(21) /* adl/dg2+ */