Commit a688efea authored by Amit Vadhavana's avatar Amit Vadhavana Committed by Vinod Koul
Browse files

dmaengine: Fix spelling mistakes 



Correct spelling mistakes in the DMA engine to improve readability
and clarity without altering functionality.

Signed-off-by: default avatarAmit Vadhavana <av2082000@gmail.com>
Reviewed-by: default avatarKees Cook <kees@kernel.org>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Reviewed-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Link: https://lore.kernel.org/r/20240831172949.13189-1-av2082000@gmail.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5d318b59

drivers/dma/acpi-dma.c

+2 −2
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ static int acpi_dma_parse_resource_group(const struct acpi_csrt_group *grp, 
}



/**

 * acpi_dma_parse_csrt - parse CSRT to exctract additional DMA resources

 * acpi_dma_parse_csrt - parse CSRT to extract additional DMA resources

 * @adev:	ACPI device to match with

 * @adma:	struct acpi_dma of the given DMA controller

 *
@@ -305,7 +305,7 @@ EXPORT_SYMBOL_GPL(devm_acpi_dma_controller_free); 
 * found.

 *

 * Return:

 * 0, if no information is avaiable, -1 on mismatch, and 1 otherwise.

 * 0, if no information is available, -1 on mismatch, and 1 otherwise.

 */

static int acpi_dma_update_dma_spec(struct acpi_dma *adma,

		struct acpi_dma_spec *dma_spec)

drivers/dma/altera-msgdma.c

+2 −2
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ struct msgdma_extended_desc { 
/**

 * struct msgdma_sw_desc - implements a sw descriptor

 * @async_tx: support for the async_tx api

 * @hw_desc: assosiated HW descriptor

 * @hw_desc: associated HW descriptor

 * @node: node to move from the free list to the tx list

 * @tx_list: transmit list node

 */
@@ -511,7 +511,7 @@ static void msgdma_copy_one(struct msgdma_device *mdev, 
	 * of the DMA controller. The descriptor will get flushed to the

	 * FIFO, once the last word (control word) is written. Since we

	 * are not 100% sure that memcpy() writes all word in the "correct"

	 * oder (address from low to high) on all architectures, we make

	 * order (address from low to high) on all architectures, we make

	 * sure this control word is written last by single coding it and

	 * adding some write-barriers here.

	 */

drivers/dma/amba-pl08x.c

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Copyright (c) 2006 ARM Ltd.

 * Copyright (c) 2010 ST-Ericsson SA

 * Copyirght (c) 2017 Linaro Ltd.

 * Copyright (c) 2017 Linaro Ltd.

 *

 * Author: Peter Pearse <peter.pearse@arm.com>

 * Author: Linus Walleij <linus.walleij@linaro.org>

drivers/dma/at_hdmac.c

+3 −3
Original line number Diff line number Diff line
@@ -339,7 +339,7 @@ static inline u8 convert_buswidth(enum dma_slave_buswidth addr_width) 
 * @regs: memory mapped register base

 * @clk: dma controller clock

 * @save_imr: interrupt mask register that is saved on suspend/resume cycle

 * @all_chan_mask: all channels availlable in a mask

 * @all_chan_mask: all channels available in a mask

 * @lli_pool: hw lli table

 * @memset_pool: hw memset pool

 * @chan: channels table to store at_dma_chan structures
@@ -668,7 +668,7 @@ static inline u32 atc_calc_bytes_left(u32 current_len, u32 ctrla) 
 * CTRLA is read in turn, next the DSCR is read a second time. If the two

 * consecutive read values of the DSCR are the same then we assume both refers

 * to the very same LLI as well as the CTRLA value read inbetween does. For

 * cyclic tranfers, the assumption is that a full loop is "not so fast". If the

 * cyclic transfers, the assumption is that a full loop is "not so fast". If the

 * two DSCR values are different, we read again the CTRLA then the DSCR till two

 * consecutive read values from DSCR are equal or till the maximum trials is

 * reach. This algorithm is very unlikely not to find a stable value for DSCR.
@@ -700,7 +700,7 @@ static int atc_get_llis_residue(struct at_dma_chan *atchan, 
			break;



		/*

		 * DSCR has changed inside the DMA controller, so the previouly

		 * DSCR has changed inside the DMA controller, so the previously

		 * read value of CTRLA may refer to an already processed

		 * descriptor hence could be outdated. We need to update ctrla

		 * to match the current descriptor.

drivers/dma/bcm-sba-raid.c

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
 * number of hardware rings over one or more SBA hardware devices. By

 * design, the internal buffer size of SBA hardware device is limited

 * but all offload operations supported by SBA can be broken down into

 * multiple small size requests and executed parallely on multiple SBA

 * multiple small size requests and executed parallelly on multiple SBA

 * hardware devices for achieving high through-put.

 *

 * The Broadcom SBA RAID driver does not require any register programming
@@ -135,7 +135,7 @@ struct sba_device { 
	u32 max_xor_srcs;

	u32 max_resp_pool_size;

	u32 max_cmds_pool_size;

	/* Maibox client and Mailbox channels */

	/* Mailbox client and Mailbox channels */

	struct mbox_client client;

	struct mbox_chan *mchan;

	struct device *mbox_dev;