Commit a6a61b97 authored by Jagadeesh Kona's avatar Jagadeesh Kona Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom: Add SM8650 video clock controller 



SM8650 video clock controller has most clocks same as SM8450,
but it also has few additional clocks and resets. Add device tree
bindings for the video clock controller on Qualcomm SM8650 platform
by defining these additional clocks and resets on top of SM8450.

Signed-off-by: default avatarJagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarVladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 213e1b58

Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml

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@@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 


maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Jagadeesh Kona <quic_jkona@quicinc.com>



description: |

  Qualcomm video clock control module provides the clocks, resets and power

  domains on SM8450.



  See also: include/dt-bindings/clock/qcom,sm8450-videocc.h

  See also:

    include/dt-bindings/clock/qcom,sm8450-videocc.h

    include/dt-bindings/clock/qcom,sm8650-videocc.h



properties:

  compatible:

    enum:

      - qcom,sm8450-videocc

      - qcom,sm8550-videocc

      - qcom,sm8650-videocc



  reg:

    maxItems: 1

include/dt-bindings/clock/qcom,sm8650-videocc.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H

#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H



#include "qcom,sm8450-videocc.h"



/* SM8650 introduces below new clocks and resets compared to SM8450 */



/* VIDEO_CC clocks */

#define VIDEO_CC_MVS0_SHIFT_CLK					12

#define VIDEO_CC_MVS0C_SHIFT_CLK				13

#define VIDEO_CC_MVS1_SHIFT_CLK					14

#define VIDEO_CC_MVS1C_SHIFT_CLK				15

#define VIDEO_CC_XO_CLK_SRC					16



/* VIDEO_CC resets */

#define VIDEO_CC_XO_CLK_ARES					7



#endif