Commit a6a9d10e authored by Sayali Lokhande's avatar Sayali Lokhande Committed by Bjorn Andersson
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arm64: dts: qcom: qcs615: add UFS node 



Add the UFS Host Controller node and its PHY for QCS615 SoC.

Signed-off-by: default avatarSayali Lokhande <quic_sayalil@quicinc.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Co-developed-by: default avatarXin Liu <quic_liuxin@quicinc.com>
Signed-off-by: default avatarXin Liu <quic_liuxin@quicinc.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241216095439.531357-3-quic_liuxin@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 113d52bd

arch/arm64/boot/dts/qcom/qcs615.dtsi

+113 −0
Original line number Diff line number Diff line
@@ -1001,6 +1001,119 @@ mmss_noc: interconnect@1740000 { 
			qcom,bcm-voters = <&apps_bcm_voter>;

		};



		ufs_mem_hc: ufshc@1d84000 {

			compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";

			reg = <0x0 0x01d84000 0x0 0x3000>,

			      <0x0 0x01d90000 0x0 0x8000>;

			reg-names = "std",

				    "ice";



			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;



			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_UFS_PHY_AHB_CLK>,

				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;

			clock-names = "core_clk",

				      "bus_aggr_clk",

				      "iface_clk",

				      "core_clk_unipro",

				      "core_clk_ice",

				      "ref_clk",

				      "tx_lane0_sync_clk",

				      "rx_lane0_sync_clk";



			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			operating-points-v2 = <&ufs_opp_table>;

			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,

					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

					 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;

			interconnect-names = "ufs-ddr",

					     "cpu-ufs";



			power-domains = <&gcc UFS_PHY_GDSC>;



			iommus = <&apps_smmu 0x300 0x0>;

			dma-coherent;



			lanes-per-direction = <1>;



			phys = <&ufs_mem_phy>;

			phy-names = "ufsphy";



			#reset-cells = <1>;



			status = "disabled";



			ufs_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-50000000 {

					opp-hz = /bits/ 64 <50000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <37500000>,

						 /bits/ 64 <75000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>;

					required-opps = <&rpmhpd_opp_low_svs>;

				};



				opp-100000000 {

					opp-hz = /bits/ 64 <100000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <75000000>,

						 /bits/ 64 <150000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>;

					required-opps = <&rpmhpd_opp_svs>;

				};



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <150000000>,

						 /bits/ 64 <300000000>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>,

						 /bits/ 64 <0>;

					required-opps = <&rpmhpd_opp_nom>;

				};

			};

		};



		ufs_mem_phy: phy@1d87000 {

			compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";

			reg = <0x0 0x01d87000 0x0 0xe00>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,

				 <&gcc GCC_UFS_MEM_CLKREF_CLK>;

			clock-names = "ref",

				      "ref_aux",

				      "qref";



			power-domains = <&gcc UFS_PHY_GDSC>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";



			#clock-cells = <1>;

			#phy-cells = <0>;



			status = "disabled";

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0x0 0x01f40000 0x0 0x20000>;