Commit a6f59c04 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: correct register Clock Gater incorrectly disabled 



[why]
The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater
when the DPP is enabled.

The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode.
This will disable the clock gater and the DPPCLK register clock branch will always be running.
As a consequence, the dynamic power will be higher than expected.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1c6b16eb

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

+4 −6
Original line number Diff line number Diff line
@@ -50,13 +50,11 @@ void dpp35_dppclk_control( 
				DPPCLK_RATE_CONTROL, dppclk_div,

				DPP_CLOCK_ENABLE, 1);

		else

			REG_UPDATE_2(DPP_CONTROL,

					DPP_CLOCK_ENABLE, 1,

					DISPCLK_R_GATE_DISABLE, 1);

			REG_UPDATE(DPP_CONTROL,

					DPP_CLOCK_ENABLE, 1);

	} else

		REG_UPDATE_2(DPP_CONTROL,

				DPP_CLOCK_ENABLE, 0,

				DISPCLK_R_GATE_DISABLE, 0);

		REG_UPDATE(DPP_CONTROL,

				DPP_CLOCK_ENABLE, 0);

}



void dpp35_program_bias_and_scale_fcnv(