Commit a794e783 authored by Ivaylo Ivanov's avatar Ivaylo Ivanov Committed by Krzysztof Kozlowski
Browse files

clk: samsung: clk-pll: Add support for pll_{1051x,1052x} 



These plls are found in the Exynos8895 SoC:
- pll1051x: Integer PLL with middle frequency
- pll1052x: Integer PLL with low frequency

The PLLs are similar enough to pll_0822x, so the same code can handle
all.

Locktime for 1051x, 1052x is 150 - the same as the pll_0822x
lock factor. MDIV, SDIV, PDIV masks and bit shifts are also the same
as 0822x.

When defining a PLL, the "con" parameter should be set to CON0
register, like this:

PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
    PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
    pll_shared0_rate_table),

Signed-off-by: default avatarIvaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023090136.537395-3-ivo.ivanov.ivanov1@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 807b1a36

drivers/clk/samsung/clk-pll.c

+2 −0
Original line number Diff line number Diff line
@@ -1370,6 +1370,8 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 
		break;

	case pll_1417x:

	case pll_1418x:

	case pll_1051x:

	case pll_1052x:

	case pll_0818x:

	case pll_0822x:

	case pll_0516x:

drivers/clk/samsung/clk-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ enum samsung_pll_type { 
	pll_0517x,

	pll_0518x,

	pll_531x,

	pll_1051x,

	pll_1052x,

};



#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \