dt-bindings: pinctrl: document the Eliza Top Level Mode Multiplexer

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Eliza TLMM block

maintainers:

  - Abel Vesa <abel.vesa@oss.qualcomm.com>

description:

  Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC.

allOf:

  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:

  compatible:

    const: qcom,eliza-tlmm

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  gpio-reserved-ranges:

    minItems: 1

    maxItems: 93

  gpio-line-names:

    maxItems: 185

patternProperties:

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-eliza-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-eliza-tlmm-state"

        additionalProperties: false

$defs:

  qcom-eliza-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.

    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state

    unevaluatedProperties: false

    properties:

      pins:

        description:

          List of gpio pins affected by the properties specified in this

          subnode.

        items:

          oneOf:

            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$"

            - enum: [ ufs_reset ]

        minItems: 1

        maxItems: 36

      function:

        description:

          Specify the alternative function to be configured for the specified

          pins.

        enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,

                audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl,

                cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx,

                coex_uart2_rx, coex_uart2_tx, dbg_out_clk,

                ddr_bist_complete, ddr_bist_fail, ddr_bist_start,

                ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio,

                gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1,

                hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1,

                hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec,

                host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,

                ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out,

                mdp_vsync, mdp_vsync0_out, mdp_vsync11_out,

                mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,

                mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,

                pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,

                pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,

                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk,

                qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,

                qlink_big_request, qlink_little_enable,

                qlink_little_request, qlink_wmss, qspi0, qspi_clk,

                qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,

                qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,

                qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,

                qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,

                sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,

                tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,

                tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,

                uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,

                uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,

                vsense_trigger_mirnat, wcn_sw_ctrl ]

    required:

      - pins

required:

  - compatible

  - reg

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    tlmm: pinctrl@f100000 {

        compatible = "qcom,eliza-tlmm";

        reg = <0x0f100000 0x300000>;

        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-controller;

        #gpio-cells = <2>;

        interrupt-controller;

        #interrupt-cells = <2>;

        gpio-ranges = <&tlmm 0 0 186>;

        gpio-wo-state {

            pins = "gpio1";

            function = "gpio";

        };

        qup-uart14-default-state {

            pins = "gpio18", "gpio19";

            function = "qup2_se5";

            drive-strength = <2>;

            bias-disable;

        };

    };

...