Commit a861e580 authored by Linu Cherian's avatar Linu Cherian Committed by Paolo Abeni
Browse files

octeontx2-af: Skip NDC operations for cn20k 



For cn20k, NPA block doesn't use the general purpose
NDC (Near Coprocessor Bus Data cache Unit) for caching,
hence skip the NDC related operations.
Also refactor NDC configuration code to a helper function.

Signed-off-by: default avatarLinu Cherian <lcherian@marvell.com>
Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Link: https://patch.msgid.link/1761388367-16579-7-git-send-email-sbhatta@marvell.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent e4a8e78a

drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c

+3 −0
Original line number Diff line number Diff line
@@ -2808,6 +2808,9 @@ static void rvu_dbg_npa_init(struct rvu *rvu) 
			    &rvu_dbg_npa_aura_ctx_fops);

	debugfs_create_file("pool_ctx", 0600, rvu->rvu_dbg.npa, rvu,

			    &rvu_dbg_npa_pool_ctx_fops);



	if (is_cn20k(rvu->pdev)) /* NDC not appliable for cn20k */

		return;

	debugfs_create_file("ndc_cache", 0600, rvu->rvu_dbg.npa, rvu,

			    &rvu_dbg_npa_ndc_cache_fops);

	debugfs_create_file("ndc_hits_miss", 0600, rvu->rvu_dbg.npa, rvu,

drivers/net/ethernet/marvell/octeontx2/af/rvu_npa.c

+21 −8
Original line number Diff line number Diff line
@@ -464,6 +464,23 @@ int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, 
	return 0;

}



static void npa_aq_ndc_config(struct rvu *rvu, struct rvu_block *block)

{

	u64 cfg;



	if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */

		return;



	/* Do not bypass NDC cache */

	cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG);

	cfg &= ~0x03DULL;

#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING

	/* Disable caching of stack pages */

	cfg |= 0x10ULL;

#endif

	rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);

}



static int npa_aq_init(struct rvu *rvu, struct rvu_block *block)

{

	u64 cfg;
@@ -479,14 +496,7 @@ static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) 
	rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg);

#endif



	/* Do not bypass NDC cache */

	cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG);

	cfg &= ~0x03DULL;

#ifdef CONFIG_NDC_DIS_DYNAMIC_CACHING

	/* Disable caching of stack pages */

	cfg |= 0x10ULL;

#endif

	rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg);

	npa_aq_ndc_config(rvu, block);



	/* For CN10K NPA BATCH DMA set 35 cache lines */

	if (!is_rvu_otx2(rvu)) {
@@ -567,6 +577,9 @@ int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr) 
	int bank, max_bank, line, max_line, err;

	u64 reg, ndc_af_const;



	if (is_cn20k(rvu->pdev)) /* NDC not applicable to cn20k */

		return 0;



	/* Set the ENABLE bit(63) to '0' */

	reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL);

	rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0));