Commit a879009f authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Update underflow detection



[WHY]
Add underflow detection for later ASICs.

Reviewed-by: default avatarLeo Chen <leo.chen@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f3d34948
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+5 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@
	uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \
	uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \
	uint32_t OTG_DLPC_CONTROL; \
	uint32_t OTG_DRR_CONTROL2; \
	uint32_t OTG_DRR_CONTOL2; \
	uint32_t OTG_DRR_TIMING_INT_STATUS; \
	uint32_t OTG_GLOBAL_CONTROL3; \
	uint32_t OTG_GLOBAL_SYNC_STATUS; \
@@ -676,6 +676,10 @@ struct dcn_optc_registers {
	type OTG_V_COUNT_STOP_TIMER;

#define TG_REG_FIELD_LIST_DCN3_6(type) \
	type OPTC_RSMU_UNDERFLOW_CLEAR;\
	type OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS;\
	type OPTC_RSMU_UNDERFLOW_INT_EN;\
	type OPTC_RSMU_UNDERFLOW_INT_STATUS;\
	type OTG_CRC_POLY_SEL; \
	type CRC0_R_CR32; \
	type CRC0_G_Y32; \
+1 −1
Original line number Diff line number Diff line
@@ -363,7 +363,7 @@ void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_st
	optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG);
	optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL);
	optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
	optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2);
	optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTOL2);
	optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL);
	optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS);
	optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW);