Commit aa66eb12 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Bartosz Golaszewski
Browse files

dt-bindings: gpio: Convert st,spear-spics-gpio to DT schema 



Convert the ST SPEAr SPI CS GPIO binding to DT schema format. It's a
straight forward conversion.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Link: https://lore.kernel.org/r/20250714202753.3010240-1-robh@kernel.org


Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent 48a9cf93

Documentation/devicetree/bindings/gpio/spear_spics.txt

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=== ST Microelectronics SPEAr SPI CS Driver ===



SPEAr platform provides a provision to control chipselects of ARM PL022 Prime

Cell spi controller through its system registers, which otherwise remains under

PL022 control. If chipselect remain under PL022 control then they would be

released as soon as transfer is over and TxFIFO becomes empty. This is not

desired by some of the device protocols above spi which expect (multiple)

transfers without releasing their chipselects.



Chipselects can be controlled by software by turning them as GPIOs. SPEAr

provides another interface through system registers through which software can

directly control each PL022 chipselect. Hence, it is natural for SPEAr to export

the control of this interface as gpio.



Required properties:



  * compatible: should be defined as "st,spear-spics-gpio"

  * reg: mentioning address range of spics controller

  * st-spics,peripcfg-reg: peripheral configuration register offset

  * st-spics,sw-enable-bit: bit offset to enable sw control

  * st-spics,cs-value-bit: bit offset to drive chipselect low or high

  * st-spics,cs-enable-mask: chip select number bit mask

  * st-spics,cs-enable-shift: chip select number program offset

  * gpio-controller: Marks the device node as gpio controller

  * #gpio-cells: should be 1 and will mention chip select number



All the above bit offsets are within peripcfg register.



Example:

-------

spics: spics@e0700000{

        compatible = "st,spear-spics-gpio";

        reg = <0xe0700000 0x1000>;

        st-spics,peripcfg-reg = <0x3b0>;

        st-spics,sw-enable-bit = <12>;

        st-spics,cs-value-bit = <11>;

        st-spics,cs-enable-mask = <3>;

        st-spics,cs-enable-shift = <8>;

        gpio-controller;

        #gpio-cells = <2>;

};





spi0: spi@e0100000 {

        num-cs = <3>;

        cs-gpios = <&gpio1 7 0>, <&spics 0>,

                   <&spics 1>;

	...

}

Documentation/devicetree/bindings/gpio/st,spear-spics-gpio.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ST Microelectronics SPEAr SPI CS GPIO Controller



maintainers:

  - Viresh Kumar <vireshk@kernel.org>



description: >

  SPEAr platform provides a provision to control chipselects of ARM PL022 Prime

  Cell spi controller through its system registers, which otherwise remains

  under PL022 control. If chipselect remain under PL022 control then they would

  be released as soon as transfer is over and TxFIFO becomes empty. This is not

  desired by some of the device protocols above spi which expect (multiple)

  transfers without releasing their chipselects.



  Chipselects can be controlled by software by turning them as GPIOs. SPEAr

  provides another interface through system registers through which software can

  directly control each PL022 chipselect. Hence, it is natural for SPEAr to

  export the control of this interface as gpio.



properties:

  compatible:

    const: st,spear-spics-gpio



  reg:

    maxItems: 1



  gpio-controller: true



  '#gpio-cells':

    const: 2



  st-spics,peripcfg-reg:

    description: Offset of the peripcfg register.

    $ref: /schemas/types.yaml#/definitions/uint32



  st-spics,sw-enable-bit:

    description: Bit offset to enable software chipselect control.

    $ref: /schemas/types.yaml#/definitions/uint32



  st-spics,cs-value-bit:

    description: Bit offset to drive chipselect low or high.

    $ref: /schemas/types.yaml#/definitions/uint32



  st-spics,cs-enable-mask:

    description: Bitmask selecting which chipselects to enable.

    $ref: /schemas/types.yaml#/definitions/uint32



  st-spics,cs-enable-shift:

    description: Bit shift for programming chipselect number.

    $ref: /schemas/types.yaml#/definitions/uint32



required:

  - compatible

  - reg

  - gpio-controller

  - '#gpio-cells'

  - st-spics,peripcfg-reg

  - st-spics,sw-enable-bit

  - st-spics,cs-value-bit

  - st-spics,cs-enable-mask

  - st-spics,cs-enable-shift



additionalProperties: false



examples:

  - |

    gpio@e0700000 {

        compatible = "st,spear-spics-gpio";

        reg = <0xe0700000 0x1000>;

        st-spics,peripcfg-reg = <0x3b0>;

        st-spics,sw-enable-bit = <12>;

        st-spics,cs-value-bit = <11>;

        st-spics,cs-enable-mask = <3>;

        st-spics,cs-enable-shift = <8>;

        gpio-controller;

        #gpio-cells = <2>;

    };