Commit aa90a308 authored by Itamar Gozlan's avatar Itamar Gozlan Committed by Jakub Kicinski
Browse files

net/mlx5: DR, expand SWS STE callbacks and consolidate common structs 



Expand SWS STE callbacks to support ConnectX-8 hardware.
Move common enums and structures to a shared header file.

Signed-off-by: default avatarItamar Gozlan <igozlan@nvidia.com>
Signed-off-by: default avatarYevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/20241219175841.1094544-9-tariqt@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 429776b6

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.c

+2 −2
Original line number Diff line number Diff line
@@ -555,7 +555,7 @@ void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, 
			       struct mlx5dr_ste_actions_attr *attr,

			       u32 *added_stes)

{

	ste_ctx->set_actions_tx(dmn, action_type_set, ste_ctx->actions_caps,

	ste_ctx->set_actions_tx(ste_ctx, dmn, action_type_set, ste_ctx->actions_caps,

				hw_ste_arr, attr, added_stes);

}
@@ -566,7 +566,7 @@ void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, 
			       struct mlx5dr_ste_actions_attr *attr,

			       u32 *added_stes)

{

	ste_ctx->set_actions_rx(dmn, action_type_set, ste_ctx->actions_caps,

	ste_ctx->set_actions_rx(ste_ctx, dmn, action_type_set, ste_ctx->actions_caps,

				hw_ste_arr, attr, added_stes);

}

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

+15 −3
Original line number Diff line number Diff line
@@ -160,13 +160,15 @@ struct mlx5dr_ste_ctx { 


	/* Actions */

	u32 actions_caps;

	void (*set_actions_rx)(struct mlx5dr_domain *dmn,

	void (*set_actions_rx)(struct mlx5dr_ste_ctx *ste_ctx,

			       struct mlx5dr_domain *dmn,

			       u8 *action_type_set,

			       u32 actions_caps,

			       u8 *hw_ste_arr,

			       struct mlx5dr_ste_actions_attr *attr,

			       u32 *added_stes);

	void (*set_actions_tx)(struct mlx5dr_domain *dmn,

	void (*set_actions_tx)(struct mlx5dr_ste_ctx *ste_ctx,

			       struct mlx5dr_domain *dmn,

			       u8 *action_type_set,

			       u32 actions_caps,

			       u8 *hw_ste_arr,
@@ -197,7 +199,17 @@ struct mlx5dr_ste_ctx { 
					u16 *used_hw_action_num);

	int (*alloc_modify_hdr_chunk)(struct mlx5dr_action *action);

	void (*dealloc_modify_hdr_chunk)(struct mlx5dr_action *action);



	/* Actions bit set */

	void (*set_encap)(u8 *hw_ste_p, u8 *d_action,

			  u32 reformat_id, int size);

	void (*set_push_vlan)(u8 *ste, u8 *d_action,

			      u32 vlan_hdr);

	void (*set_pop_vlan)(u8 *hw_ste_p, u8 *s_action,

			     u8 vlans_num);

	void (*set_rx_decap)(u8 *hw_ste_p, u8 *s_action);

	void (*set_encap_l3)(u8 *hw_ste_p, u8 *frst_s_action,

			     u8 *scnd_d_action, u32 reformat_id,

			     int size);

	/* Send */

	void (*prepare_for_postsend)(u8 *hw_ste_p, u32 ste_size);

};

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v0.c

+4 −2
Original line number Diff line number Diff line
@@ -406,7 +406,8 @@ static void dr_ste_v0_arr_init_next(u8 **last_ste, 
}



static void

dr_ste_v0_set_actions_tx(struct mlx5dr_domain *dmn,

dr_ste_v0_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx,

			 struct mlx5dr_domain *dmn,

			 u8 *action_type_set,

			 u32 actions_caps,

			 u8 *last_ste,
@@ -476,7 +477,8 @@ dr_ste_v0_set_actions_tx(struct mlx5dr_domain *dmn, 
}



static void

dr_ste_v0_set_actions_rx(struct mlx5dr_domain *dmn,

dr_ste_v0_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx,

			 struct mlx5dr_domain *dmn,

			 u8 *action_type_set,

			 u32 actions_caps,

			 u8 *last_ste,

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v1.c

+38 −169
Original line number Diff line number Diff line
@@ -5,136 +5,6 @@ 
#include "mlx5_ifc_dr_ste_v1.h"

#include "dr_ste_v1.h"



#define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \

	((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \

		   DR_STE_V1_LU_TYPE_##lookup_type##_O)



enum dr_ste_v1_entry_format {

	DR_STE_V1_TYPE_BWC_BYTE	= 0x0,

	DR_STE_V1_TYPE_BWC_DW	= 0x1,

	DR_STE_V1_TYPE_MATCH	= 0x2,

	DR_STE_V1_TYPE_MATCH_RANGES = 0x7,

};



/* Lookup type is built from 2B: [ Definer mode 1B ][ Definer index 1B ] */

enum {

	DR_STE_V1_LU_TYPE_NOP				= 0x0000,

	DR_STE_V1_LU_TYPE_ETHL2_TNL			= 0x0002,

	DR_STE_V1_LU_TYPE_IBL3_EXT			= 0x0102,

	DR_STE_V1_LU_TYPE_ETHL2_O			= 0x0003,

	DR_STE_V1_LU_TYPE_IBL4				= 0x0103,

	DR_STE_V1_LU_TYPE_ETHL2_I			= 0x0004,

	DR_STE_V1_LU_TYPE_SRC_QP_GVMI			= 0x0104,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_O			= 0x0005,

	DR_STE_V1_LU_TYPE_ETHL2_HEADERS_O		= 0x0105,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_I			= 0x0006,

	DR_STE_V1_LU_TYPE_ETHL2_HEADERS_I		= 0x0106,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_O		= 0x0007,

	DR_STE_V1_LU_TYPE_IPV6_DES_O			= 0x0107,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_I		= 0x0008,

	DR_STE_V1_LU_TYPE_IPV6_DES_I			= 0x0108,

	DR_STE_V1_LU_TYPE_ETHL4_O			= 0x0009,

	DR_STE_V1_LU_TYPE_IPV6_SRC_O			= 0x0109,

	DR_STE_V1_LU_TYPE_ETHL4_I			= 0x000a,

	DR_STE_V1_LU_TYPE_IPV6_SRC_I			= 0x010a,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_O		= 0x000b,

	DR_STE_V1_LU_TYPE_MPLS_O			= 0x010b,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_I		= 0x000c,

	DR_STE_V1_LU_TYPE_MPLS_I			= 0x010c,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_O		= 0x000d,

	DR_STE_V1_LU_TYPE_GRE				= 0x010d,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER	= 0x000e,

	DR_STE_V1_LU_TYPE_GENERAL_PURPOSE		= 0x010e,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I		= 0x000f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0		= 0x010f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1		= 0x0110,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_OK		= 0x0011,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_0			= 0x0111,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_1			= 0x0112,

	DR_STE_V1_LU_TYPE_ETHL4_MISC_O			= 0x0113,

	DR_STE_V1_LU_TYPE_ETHL4_MISC_I			= 0x0114,

	DR_STE_V1_LU_TYPE_INVALID			= 0x00ff,

	DR_STE_V1_LU_TYPE_DONT_CARE			= MLX5DR_STE_LU_TYPE_DONT_CARE,

};



enum dr_ste_v1_header_anchors {

	DR_STE_HEADER_ANCHOR_START_OUTER		= 0x00,

	DR_STE_HEADER_ANCHOR_1ST_VLAN			= 0x02,

	DR_STE_HEADER_ANCHOR_IPV6_IPV4			= 0x07,

	DR_STE_HEADER_ANCHOR_INNER_MAC			= 0x13,

	DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4		= 0x19,

};



enum dr_ste_v1_action_size {

	DR_STE_ACTION_SINGLE_SZ = 4,

	DR_STE_ACTION_DOUBLE_SZ = 8,

	DR_STE_ACTION_TRIPLE_SZ = 12,

};



enum dr_ste_v1_action_insert_ptr_attr {

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE = 0,  /* Regular push header (e.g. push vlan) */

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP = 1, /* Encapsulation / Tunneling */

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_ESP = 2,   /* IPsec */

};



enum dr_ste_v1_action_id {

	DR_STE_V1_ACTION_ID_NOP				= 0x00,

	DR_STE_V1_ACTION_ID_COPY			= 0x05,

	DR_STE_V1_ACTION_ID_SET				= 0x06,

	DR_STE_V1_ACTION_ID_ADD				= 0x07,

	DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE		= 0x08,

	DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER	= 0x09,

	DR_STE_V1_ACTION_ID_INSERT_INLINE		= 0x0a,

	DR_STE_V1_ACTION_ID_INSERT_POINTER		= 0x0b,

	DR_STE_V1_ACTION_ID_FLOW_TAG			= 0x0c,

	DR_STE_V1_ACTION_ID_QUEUE_ID_SEL		= 0x0d,

	DR_STE_V1_ACTION_ID_ACCELERATED_LIST		= 0x0e,

	DR_STE_V1_ACTION_ID_MODIFY_LIST			= 0x0f,

	DR_STE_V1_ACTION_ID_ASO				= 0x12,

	DR_STE_V1_ACTION_ID_TRAILER			= 0x13,

	DR_STE_V1_ACTION_ID_COUNTER_ID			= 0x14,

	DR_STE_V1_ACTION_ID_MAX				= 0x21,

	/* use for special cases */

	DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3		= 0x22,

};



enum {

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0		= 0x00,

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1		= 0x01,

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2		= 0x02,

	DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0		= 0x08,

	DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1		= 0x09,

	DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0		= 0x0e,

	DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0		= 0x18,

	DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1		= 0x19,

	DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0		= 0x40,

	DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1		= 0x41,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0	= 0x44,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1	= 0x45,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2	= 0x46,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3	= 0x47,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0	= 0x4c,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1	= 0x4d,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2	= 0x4e,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3	= 0x4f,

	DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0		= 0x5e,

	DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1		= 0x5f,

	DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_0		= 0x6f,

	DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_1		= 0x70,

	DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE	= 0x7b,

	DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE		= 0x7c,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_0		= 0x8c,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_1		= 0x8d,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_0		= 0x8e,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_1		= 0x8f,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_0		= 0x90,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_1		= 0x91,

};



enum dr_ste_v1_aso_ctx_type {

	DR_STE_V1_ASO_CTX_TYPE_POLICERS = 0x2,

};



static const struct mlx5dr_ste_action_modify_field dr_ste_v1_action_modify_field_arr[] = {

	[MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {

		.hw_field = DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31,
@@ -379,13 +249,12 @@ static void dr_ste_v1_set_counter_id(u8 *hw_ste_p, u32 ctr_id) 
	MLX5_SET(ste_match_bwc_v1, hw_ste_p, counter_id, ctr_id);

}



static void dr_ste_v1_set_reparse(u8 *hw_ste_p)

void dr_ste_v1_set_reparse(u8 *hw_ste_p)

{

	MLX5_SET(ste_match_bwc_v1, hw_ste_p, reparse, 1);

}



static void dr_ste_v1_set_encap(u8 *hw_ste_p, u8 *d_action,

				u32 reformat_id, int size)

void dr_ste_v1_set_encap(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, int size)

{

	MLX5_SET(ste_double_action_insert_with_ptr_v1, d_action, action_id,

		 DR_STE_V1_ACTION_ID_INSERT_POINTER);
@@ -432,8 +301,7 @@ static void dr_ste_v1_set_remove_hdr(u8 *hw_ste_p, u8 *s_action, 
	dr_ste_v1_set_reparse(hw_ste_p);

}



static void dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action,

				    u32 vlan_hdr)

void dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action, u32 vlan_hdr)

{

	MLX5_SET(ste_double_action_insert_with_inline_v1, d_action,

		 action_id, DR_STE_V1_ACTION_ID_INSERT_INLINE);
@@ -446,7 +314,7 @@ static void dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action, 
	dr_ste_v1_set_reparse(hw_ste_p);

}



static void dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num)

void dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num)

{

	MLX5_SET(ste_single_action_remove_header_size_v1, s_action,

		 action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
@@ -459,11 +327,8 @@ static void dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num) 
	dr_ste_v1_set_reparse(hw_ste_p);

}



static void dr_ste_v1_set_encap_l3(u8 *hw_ste_p,

				   u8 *frst_s_action,

				   u8 *scnd_d_action,

				   u32 reformat_id,

				   int size)

void dr_ste_v1_set_encap_l3(u8 *hw_ste_p, u8 *frst_s_action, u8 *scnd_d_action,

			    u32 reformat_id, int size)

{

	/* Remove L2 headers */

	MLX5_SET(ste_single_action_remove_header_v1, frst_s_action, action_id,
@@ -483,7 +348,7 @@ static void dr_ste_v1_set_encap_l3(u8 *hw_ste_p, 
	dr_ste_v1_set_reparse(hw_ste_p);

}



static void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action)

void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action)

{

	MLX5_SET(ste_single_action_remove_header_v1, s_action, action_id,

		 DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
@@ -620,7 +485,8 @@ static void dr_ste_v1_arr_init_next_match_range(u8 **last_ste, 
	dr_ste_v1_set_entry_type(*last_ste, DR_STE_V1_TYPE_MATCH_RANGES);

}



void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn,

void dr_ste_v1_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx,

			      struct mlx5dr_domain *dmn,

			      u8 *action_type_set,

			      u32 actions_caps,

			      u8 *last_ste,
@@ -640,7 +506,7 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, 
					      last_ste, action);

			action_sz = DR_STE_ACTION_TRIPLE_SZ;

		}

		dr_ste_v1_set_pop_vlan(last_ste, action, attr->vlans.count);

		ste_ctx->set_pop_vlan(last_ste, action, attr->vlans.count);

		action_sz -= DR_STE_ACTION_SINGLE_SZ;

		action += DR_STE_ACTION_SINGLE_SZ;
@@ -677,7 +543,7 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, 
				action_sz = DR_STE_ACTION_TRIPLE_SZ;

				allow_encap = true;

			}

			dr_ste_v1_set_push_vlan(last_ste, action,

			ste_ctx->set_push_vlan(last_ste, action,

					       attr->vlans.headers[i]);

			action_sz -= DR_STE_ACTION_DOUBLE_SZ;

			action += DR_STE_ACTION_DOUBLE_SZ;
@@ -691,7 +557,7 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, 
			action_sz = DR_STE_ACTION_TRIPLE_SZ;

			allow_encap = true;

		}

		dr_ste_v1_set_encap(last_ste, action,

		ste_ctx->set_encap(last_ste, action,

				   attr->reformat.id,

				   attr->reformat.size);

		action_sz -= DR_STE_ACTION_DOUBLE_SZ;
@@ -706,7 +572,7 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, 
		}

		d_action = action + DR_STE_ACTION_SINGLE_SZ;



		dr_ste_v1_set_encap_l3(last_ste,

		ste_ctx->set_encap_l3(last_ste,

				      action, d_action,

				      attr->reformat.id,

				      attr->reformat.size);
@@ -776,7 +642,8 @@ void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, 
	dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);

}



void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn,

void dr_ste_v1_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx,

			      struct mlx5dr_domain *dmn,

			      u8 *action_type_set,

			      u32 actions_caps,

			      u8 *last_ste,
@@ -799,7 +666,7 @@ void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, 
		allow_modify_hdr = false;

		allow_ctr = false;

	} else if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2]) {

		dr_ste_v1_set_rx_decap(last_ste, action);

		ste_ctx->set_rx_decap(last_ste, action);

		action_sz -= DR_STE_ACTION_SINGLE_SZ;

		action += DR_STE_ACTION_SINGLE_SZ;

		allow_modify_hdr = false;
@@ -827,7 +694,7 @@ void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, 
			action_sz = DR_STE_ACTION_TRIPLE_SZ;

		}



		dr_ste_v1_set_pop_vlan(last_ste, action, attr->vlans.count);

		ste_ctx->set_pop_vlan(last_ste, action, attr->vlans.count);

		action_sz -= DR_STE_ACTION_SINGLE_SZ;

		action += DR_STE_ACTION_SINGLE_SZ;

		allow_ctr = false;
@@ -868,7 +735,7 @@ void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, 
						      last_ste, action);

				action_sz = DR_STE_ACTION_TRIPLE_SZ;

			}

			dr_ste_v1_set_push_vlan(last_ste, action,

			ste_ctx->set_push_vlan(last_ste, action,

					       attr->vlans.headers[i]);

			action_sz -= DR_STE_ACTION_DOUBLE_SZ;

			action += DR_STE_ACTION_DOUBLE_SZ;
@@ -895,7 +762,7 @@ void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, 
			action = MLX5_ADDR_OF(ste_mask_and_match_v1, last_ste, action);

			action_sz = DR_STE_ACTION_TRIPLE_SZ;

		}

		dr_ste_v1_set_encap(last_ste, action,

		ste_ctx->set_encap(last_ste, action,

				   attr->reformat.id,

				   attr->reformat.size);

		action_sz -= DR_STE_ACTION_DOUBLE_SZ;
@@ -912,7 +779,7 @@ void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, 


		d_action = action + DR_STE_ACTION_SINGLE_SZ;



		dr_ste_v1_set_encap_l3(last_ste,

		ste_ctx->set_encap_l3(last_ste,

				      action, d_action,

				      attr->reformat.id,

				      attr->reformat.size);
@@ -1027,9 +894,6 @@ void dr_ste_v1_set_action_copy(u8 *d_action, 
	MLX5_SET(ste_double_action_copy_v1, d_action, source_right_shifter, src_shifter);

}



#define DR_STE_DECAP_L3_ACTION_NUM	8

#define DR_STE_L2_HDR_MAX_SZ		20



int dr_ste_v1_set_action_decap_l3_list(void *data,

				       u32 data_sz,

				       u8 *hw_action,
@@ -2330,7 +2194,12 @@ static struct mlx5dr_ste_ctx ste_ctx_v1 = { 
	.set_action_decap_l3_list	= &dr_ste_v1_set_action_decap_l3_list,

	.alloc_modify_hdr_chunk		= &dr_ste_v1_alloc_modify_hdr_ptrn_arg,

	.dealloc_modify_hdr_chunk	= &dr_ste_v1_free_modify_hdr_ptrn_arg,



	/* Actions bit set */

	.set_encap			= &dr_ste_v1_set_encap,

	.set_push_vlan			= &dr_ste_v1_set_push_vlan,

	.set_pop_vlan			= &dr_ste_v1_set_pop_vlan,

	.set_rx_decap			= &dr_ste_v1_set_rx_decap,

	.set_encap_l3			= &dr_ste_v1_set_encap_l3,

	/* Send */

	.prepare_for_postsend		= &dr_ste_v1_prepare_for_postsend,

};

drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v1.h

+143 −4
Original line number Diff line number Diff line
@@ -7,6 +7,138 @@ 
#include "dr_types.h"

#include "dr_ste.h"



#define DR_STE_DECAP_L3_ACTION_NUM	8

#define DR_STE_L2_HDR_MAX_SZ		20

#define DR_STE_CALC_DFNR_TYPE(lookup_type, inner) \

	((inner) ? DR_STE_V1_LU_TYPE_##lookup_type##_I : \

		   DR_STE_V1_LU_TYPE_##lookup_type##_O)



enum dr_ste_v1_entry_format {

	DR_STE_V1_TYPE_BWC_BYTE	= 0x0,

	DR_STE_V1_TYPE_BWC_DW	= 0x1,

	DR_STE_V1_TYPE_MATCH	= 0x2,

	DR_STE_V1_TYPE_MATCH_RANGES = 0x7,

};



/* Lookup type is built from 2B: [ Definer mode 1B ][ Definer index 1B ] */

enum {

	DR_STE_V1_LU_TYPE_NOP				= 0x0000,

	DR_STE_V1_LU_TYPE_ETHL2_TNL			= 0x0002,

	DR_STE_V1_LU_TYPE_IBL3_EXT			= 0x0102,

	DR_STE_V1_LU_TYPE_ETHL2_O			= 0x0003,

	DR_STE_V1_LU_TYPE_IBL4				= 0x0103,

	DR_STE_V1_LU_TYPE_ETHL2_I			= 0x0004,

	DR_STE_V1_LU_TYPE_SRC_QP_GVMI			= 0x0104,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_O			= 0x0005,

	DR_STE_V1_LU_TYPE_ETHL2_HEADERS_O		= 0x0105,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_I			= 0x0006,

	DR_STE_V1_LU_TYPE_ETHL2_HEADERS_I		= 0x0106,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_O		= 0x0007,

	DR_STE_V1_LU_TYPE_IPV6_DES_O			= 0x0107,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_5_TUPLE_I		= 0x0008,

	DR_STE_V1_LU_TYPE_IPV6_DES_I			= 0x0108,

	DR_STE_V1_LU_TYPE_ETHL4_O			= 0x0009,

	DR_STE_V1_LU_TYPE_IPV6_SRC_O			= 0x0109,

	DR_STE_V1_LU_TYPE_ETHL4_I			= 0x000a,

	DR_STE_V1_LU_TYPE_IPV6_SRC_I			= 0x010a,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_O		= 0x000b,

	DR_STE_V1_LU_TYPE_MPLS_O			= 0x010b,

	DR_STE_V1_LU_TYPE_ETHL2_SRC_DST_I		= 0x000c,

	DR_STE_V1_LU_TYPE_MPLS_I			= 0x010c,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_O		= 0x000d,

	DR_STE_V1_LU_TYPE_GRE				= 0x010d,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_TNL_HEADER	= 0x000e,

	DR_STE_V1_LU_TYPE_GENERAL_PURPOSE		= 0x010e,

	DR_STE_V1_LU_TYPE_ETHL3_IPV4_MISC_I		= 0x000f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_0		= 0x010f,

	DR_STE_V1_LU_TYPE_STEERING_REGISTERS_1		= 0x0110,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_OK		= 0x0011,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_0			= 0x0111,

	DR_STE_V1_LU_TYPE_FLEX_PARSER_1			= 0x0112,

	DR_STE_V1_LU_TYPE_ETHL4_MISC_O			= 0x0113,

	DR_STE_V1_LU_TYPE_ETHL4_MISC_I			= 0x0114,

	DR_STE_V1_LU_TYPE_INVALID			= 0x00ff,

	DR_STE_V1_LU_TYPE_DONT_CARE			= MLX5DR_STE_LU_TYPE_DONT_CARE,

};



enum dr_ste_v1_header_anchors {

	DR_STE_HEADER_ANCHOR_START_OUTER		= 0x00,

	DR_STE_HEADER_ANCHOR_1ST_VLAN			= 0x02,

	DR_STE_HEADER_ANCHOR_IPV6_IPV4			= 0x07,

	DR_STE_HEADER_ANCHOR_INNER_MAC			= 0x13,

	DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4		= 0x19,

};



enum dr_ste_v1_action_size {

	DR_STE_ACTION_SINGLE_SZ = 4,

	DR_STE_ACTION_DOUBLE_SZ = 8,

	DR_STE_ACTION_TRIPLE_SZ = 12,

};



enum dr_ste_v1_action_insert_ptr_attr {

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_NONE = 0,  /* Regular push header (e.g. push vlan) */

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP = 1, /* Encapsulation / Tunneling */

	DR_STE_V1_ACTION_INSERT_PTR_ATTR_ESP = 2,   /* IPsec */

};



enum dr_ste_v1_action_id {

	DR_STE_V1_ACTION_ID_NOP				= 0x00,

	DR_STE_V1_ACTION_ID_COPY			= 0x05,

	DR_STE_V1_ACTION_ID_SET				= 0x06,

	DR_STE_V1_ACTION_ID_ADD				= 0x07,

	DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE		= 0x08,

	DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER	= 0x09,

	DR_STE_V1_ACTION_ID_INSERT_INLINE		= 0x0a,

	DR_STE_V1_ACTION_ID_INSERT_POINTER		= 0x0b,

	DR_STE_V1_ACTION_ID_FLOW_TAG			= 0x0c,

	DR_STE_V1_ACTION_ID_QUEUE_ID_SEL		= 0x0d,

	DR_STE_V1_ACTION_ID_ACCELERATED_LIST		= 0x0e,

	DR_STE_V1_ACTION_ID_MODIFY_LIST			= 0x0f,

	DR_STE_V1_ACTION_ID_ASO				= 0x12,

	DR_STE_V1_ACTION_ID_TRAILER			= 0x13,

	DR_STE_V1_ACTION_ID_COUNTER_ID			= 0x14,

	DR_STE_V1_ACTION_ID_MAX				= 0x21,

	/* use for special cases */

	DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3		= 0x22,

};



enum {

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0		= 0x00,

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1		= 0x01,

	DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2		= 0x02,

	DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0		= 0x08,

	DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1		= 0x09,

	DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0		= 0x0e,

	DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0		= 0x18,

	DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1		= 0x19,

	DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0		= 0x40,

	DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1		= 0x41,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0	= 0x44,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1	= 0x45,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2	= 0x46,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3	= 0x47,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0	= 0x4c,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1	= 0x4d,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2	= 0x4e,

	DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3	= 0x4f,

	DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0		= 0x5e,

	DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1		= 0x5f,

	DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_0		= 0x6f,

	DR_STE_V1_ACTION_MDFY_FLD_CFG_HDR_0_1		= 0x70,

	DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE	= 0x7b,

	DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE		= 0x7c,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_0		= 0x8c,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2_1		= 0x8d,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_0		= 0x8e,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_1_1		= 0x8f,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_0		= 0x90,

	DR_STE_V1_ACTION_MDFY_FLD_REGISTER_0_1		= 0x91,

};



enum dr_ste_v1_aso_ctx_type {

	DR_STE_V1_ASO_CTX_TYPE_POLICERS = 0x2,

};



bool dr_ste_v1_is_miss_addr_set(u8 *hw_ste_p);

void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr);

u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p);
@@ -17,11 +149,18 @@ u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p); 
void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size);

void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, bool is_rx, u16 gvmi);

void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, u32 ste_size);

void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, u8 *action_type_set,

			      u32 actions_caps, u8 *last_ste,

void dr_ste_v1_set_reparse(u8 *hw_ste_p);

void dr_ste_v1_set_encap(u8 *hw_ste_p, u8 *d_action, u32 reformat_id, int size);

void dr_ste_v1_set_push_vlan(u8 *hw_ste_p, u8 *d_action, u32 vlan_hdr);

void dr_ste_v1_set_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num);

void dr_ste_v1_set_encap_l3(u8 *hw_ste_p, u8 *frst_s_action, u8 *scnd_d_action,

			    u32 reformat_id, int size);

void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action);

void dr_ste_v1_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_domain *dmn,

			      u8 *action_type_set, u32 actions_caps, u8 *last_ste,

			      struct mlx5dr_ste_actions_attr *attr, u32 *added_stes);

void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, u8 *action_type_set,

			      u32 actions_caps, u8 *last_ste,

void dr_ste_v1_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, struct mlx5dr_domain *dmn,

			      u8 *action_type_set, u32 actions_caps, u8 *last_ste,

			      struct mlx5dr_ste_actions_attr *attr, u32 *added_stes);

void dr_ste_v1_set_action_set(u8 *d_action, u8 hw_field, u8 shifter,

			      u8 length, u32 data);