Commit acf2b314 authored by Uwe Kleine-König's avatar Uwe Kleine-König
Browse files

Merge tag 'pwm/duty_offset-for-6.13-rc1' of... 

Merge tag 'pwm/duty_offset-for-6.13-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux

pwm: Support for duty_offset

Support a new abstraction for pwm configuration that allows to specify
the time between start of period and the raising edge of the signal
("duty offset").

This is used in a patch series by Trevor Gamblin for triggering an ADC
conversion and afterwards read out the result. See
https://lore.kernel.org/linux-iio/20240909-ad7625_r1-v5-0-60a397768b25@baylibre.com/
for more details.
parents 22f032c7 9c918959

drivers/pwm/core.c

+705 −152

File changed.

Preview size limit exceeded, changes collapsed.

drivers/pwm/pwm-axi-pwmgen.c

+105 −43
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/err.h>

#include <linux/fpga/adi-axi-common.h>

#include <linux/io.h>

#include <linux/minmax.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/pwm.h>
@@ -53,86 +54,147 @@ static const struct regmap_config axi_pwmgen_regmap_config = { 
	.max_register = 0xFC,

};



/* This represents a hardware configuration for one channel */

struct axi_pwmgen_waveform {

	u32 period_cnt;

	u32 duty_cycle_cnt;

	u32 duty_offset_cnt;

};



static struct axi_pwmgen_ddata *axi_pwmgen_ddata_from_chip(struct pwm_chip *chip)

{

	return pwmchip_get_drvdata(chip);

}



static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm,

			    const struct pwm_state *state)

static int axi_pwmgen_round_waveform_tohw(struct pwm_chip *chip,

					  struct pwm_device *pwm,

					  const struct pwm_waveform *wf,

					  void *_wfhw)

{

	struct axi_pwmgen_waveform *wfhw = _wfhw;

	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);

	unsigned int ch = pwm->hwpwm;

	struct regmap *regmap = ddata->regmap;

	u64 period_cnt, duty_cnt;

	int ret;



	if (state->polarity != PWM_POLARITY_NORMAL)

		return -EINVAL;

	if (wf->period_length_ns == 0) {

		*wfhw = (struct axi_pwmgen_waveform){

			.period_cnt = 0,

			.duty_cycle_cnt = 0,

			.duty_offset_cnt = 0,

		};

	} else {

		/* With ddata->clk_rate_hz < NSEC_PER_SEC this won't overflow. */

		wfhw->period_cnt = min_t(u64,

					 mul_u64_u32_div(wf->period_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

					 U32_MAX);



	if (state->enabled) {

		period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC);

		if (period_cnt > UINT_MAX)

			period_cnt = UINT_MAX;

		if (wfhw->period_cnt == 0) {

			/*

			 * The specified period is too short for the hardware.

			 * Let's round .duty_cycle down to 0 to get a (somewhat)

			 * valid result.

			 */

			wfhw->period_cnt = 1;

			wfhw->duty_cycle_cnt = 0;

			wfhw->duty_offset_cnt = 0;

		} else {

			wfhw->duty_cycle_cnt = min_t(u64,

						     mul_u64_u32_div(wf->duty_length_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

						     U32_MAX);

			wfhw->duty_offset_cnt = min_t(u64,

						      mul_u64_u32_div(wf->duty_offset_ns, ddata->clk_rate_hz, NSEC_PER_SEC),

						      U32_MAX);

		}

	}



		if (period_cnt == 0)

			return -EINVAL;

	dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> PERIOD: %08x, DUTY: %08x, OFFSET: %08x\n",

		pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,

		ddata->clk_rate_hz, wfhw->period_cnt, wfhw->duty_cycle_cnt, wfhw->duty_offset_cnt);



		ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), period_cnt);

		if (ret)

			return ret;

	return 0;

}



static int axi_pwmgen_round_waveform_fromhw(struct pwm_chip *chip, struct pwm_device *pwm,

					     const void *_wfhw, struct pwm_waveform *wf)

{

	const struct axi_pwmgen_waveform *wfhw = _wfhw;

	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);



		duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC);

		if (duty_cnt > UINT_MAX)

			duty_cnt = UINT_MAX;

	wf->period_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->period_cnt * NSEC_PER_SEC,

					ddata->clk_rate_hz);



		ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt);

	wf->duty_length_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_cycle_cnt * NSEC_PER_SEC,

					    ddata->clk_rate_hz);



	wf->duty_offset_ns = DIV64_U64_ROUND_UP((u64)wfhw->duty_offset_cnt * NSEC_PER_SEC,

					     ddata->clk_rate_hz);



	return 0;

}



static int axi_pwmgen_write_waveform(struct pwm_chip *chip,

				     struct pwm_device *pwm,

				     const void *_wfhw)

{

	const struct axi_pwmgen_waveform *wfhw = _wfhw;

	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);

	struct regmap *regmap = ddata->regmap;

	unsigned int ch = pwm->hwpwm;

	int ret;



	ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), wfhw->period_cnt);

	if (ret)

		return ret;

	} else {

		ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0);



	ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), wfhw->duty_cycle_cnt);

	if (ret)

		return ret;



		ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0);

	ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), wfhw->duty_offset_cnt);

	if (ret)

		return ret;

	}



	return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG);

}



static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm,

				struct pwm_state *state)

static int axi_pwmgen_read_waveform(struct pwm_chip *chip,

				    struct pwm_device *pwm,

				    void *_wfhw)

{

	struct axi_pwmgen_waveform *wfhw = _wfhw;

	struct axi_pwmgen_ddata *ddata = axi_pwmgen_ddata_from_chip(chip);

	struct regmap *regmap = ddata->regmap;

	unsigned int ch = pwm->hwpwm;

	u32 cnt;

	int ret;



	ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &cnt);

	ret = regmap_read(regmap, AXI_PWMGEN_CHX_PERIOD(ch), &wfhw->period_cnt);

	if (ret)

		return ret;



	state->enabled = cnt != 0;



	state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);

	ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &wfhw->duty_cycle_cnt);

	if (ret)

		return ret;



	ret = regmap_read(regmap, AXI_PWMGEN_CHX_DUTY(ch), &cnt);

	ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &wfhw->duty_offset_cnt);

	if (ret)

		return ret;



	state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz);

	if (wfhw->duty_cycle_cnt > wfhw->period_cnt)

		wfhw->duty_cycle_cnt = wfhw->period_cnt;



	state->polarity = PWM_POLARITY_NORMAL;

	/* XXX: is this the actual behaviour of the hardware? */

	if (wfhw->duty_offset_cnt >= wfhw->period_cnt) {

		wfhw->duty_cycle_cnt = 0;

		wfhw->duty_offset_cnt = 0;

	}



	return 0;

}



static const struct pwm_ops axi_pwmgen_pwm_ops = {

	.apply = axi_pwmgen_apply,

	.get_state = axi_pwmgen_get_state,

	.sizeof_wfhw = sizeof(struct axi_pwmgen_waveform),

	.round_waveform_tohw = axi_pwmgen_round_waveform_tohw,

	.round_waveform_fromhw = axi_pwmgen_round_waveform_fromhw,

	.read_waveform = axi_pwmgen_read_waveform,

	.write_waveform = axi_pwmgen_write_waveform,

};



static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)

drivers/pwm/pwm-stm32.c

+391 −221
Original line number Diff line number Diff line
@@ -51,6 +51,391 @@ static u32 active_channels(struct stm32_pwm *dev) 
	return ccer & TIM_CCER_CCXE;

}



struct stm32_pwm_waveform {

	u32 ccer;

	u32 psc;

	u32 arr;

	u32 ccr;

};



static int stm32_pwm_round_waveform_tohw(struct pwm_chip *chip,

					 struct pwm_device *pwm,

					 const struct pwm_waveform *wf,

					 void *_wfhw)

{

	struct stm32_pwm_waveform *wfhw = _wfhw;

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	unsigned int ch = pwm->hwpwm;

	unsigned long rate;

	u64 ccr, duty;

	int ret;



	if (wf->period_length_ns == 0) {

		*wfhw = (struct stm32_pwm_waveform){

			.ccer = 0,

		};



		return 0;

	}



	ret = clk_enable(priv->clk);

	if (ret)

		return ret;



	wfhw->ccer = TIM_CCER_CCxE(ch + 1);

	if (priv->have_complementary_output)

		wfhw->ccer = TIM_CCER_CCxNE(ch + 1);



	rate = clk_get_rate(priv->clk);



	if (active_channels(priv) & ~(1 << ch * 4)) {

		u64 arr;



		/*

		 * Other channels are already enabled, so the configured PSC and

		 * ARR must be used for this channel, too.

		 */

		ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);

		if (ret)

			goto out;



		ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);

		if (ret)

			goto out;



		/*

		 * calculate the best value for ARR for the given PSC, refuse if

		 * the resulting period gets bigger than the requested one.

		 */

		arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,

					  (u64)NSEC_PER_SEC * (wfhw->psc + 1));

		if (arr <= wfhw->arr) {

			/*

			 * requested period is small than the currently

			 * configured and unchangable period, report back the smallest

			 * possible period, i.e. the current state; Initialize

			 * ccr to anything valid.

			 */

			wfhw->ccr = 0;

			ret = 1;

			goto out;

		}



	} else {

		/*

		 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so

		 * the calculations here won't overflow.

		 * First we need to find the minimal value for prescaler such that

		 *

		 *        period_ns * clkrate

		 *   ------------------------------ < max_arr + 1

		 *   NSEC_PER_SEC * (prescaler + 1)

		 *

		 * This equation is equivalent to

		 *

		 *        period_ns * clkrate

		 *   ---------------------------- < prescaler + 1

		 *   NSEC_PER_SEC * (max_arr + 1)

		 *

		 * Using integer division and knowing that the right hand side is

		 * integer, this is further equivalent to

		 *

		 *   (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler

		 */

		u64 psc = mul_u64_u64_div_u64(wf->period_length_ns, rate,

					      (u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));

		u64 arr;



		wfhw->psc = min_t(u64, psc, MAX_TIM_PSC);



		arr = mul_u64_u64_div_u64(wf->period_length_ns, rate,

					  (u64)NSEC_PER_SEC * (wfhw->psc + 1));

		if (!arr) {

			/*

			 * requested period is too small, report back the smallest

			 * possible period, i.e. ARR = 0. The only valid CCR

			 * value is then zero, too.

			 */

			wfhw->arr = 0;

			wfhw->ccr = 0;

			ret = 1;

			goto out;

		}



		/*

		 * ARR is limited intentionally to values less than

		 * priv->max_arr to allow 100% duty cycle.

		 */

		wfhw->arr = min_t(u64, arr, priv->max_arr) - 1;

	}



	duty = mul_u64_u64_div_u64(wf->duty_length_ns, rate,

				   (u64)NSEC_PER_SEC * (wfhw->psc + 1));

	duty = min_t(u64, duty, wfhw->arr + 1);



	if (wf->duty_length_ns && wf->duty_offset_ns &&

	    wf->duty_length_ns + wf->duty_offset_ns >= wf->period_length_ns) {

		wfhw->ccer |= TIM_CCER_CCxP(ch + 1);

		if (priv->have_complementary_output)

			wfhw->ccer |= TIM_CCER_CCxNP(ch + 1);



		ccr = wfhw->arr + 1 - duty;

	} else {

		ccr = duty;

	}



	wfhw->ccr = min_t(u64, ccr, wfhw->arr + 1);



	dev_dbg(&chip->dev, "pwm#%u: %lld/%lld [+%lld] @%lu -> CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x\n",

		pwm->hwpwm, wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns,

		rate, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr);



out:

	clk_disable(priv->clk);



	return ret;

}



/*

 * This should be moved to lib/math/div64.c. Currently there are some changes

 * pending to mul_u64_u64_div_u64. Uwe will care for that when the dust settles.

 */

static u64 stm32_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b, u64 c)

{

	u64 res = mul_u64_u64_div_u64(a, b, c);

	/* Those multiplications might overflow but it doesn't matter */

	u64 rem = a * b - c * res;



	if (rem)

		res += 1;



	return res;

}



static int stm32_pwm_round_waveform_fromhw(struct pwm_chip *chip,

					   struct pwm_device *pwm,

					   const void *_wfhw,

					   struct pwm_waveform *wf)

{

	const struct stm32_pwm_waveform *wfhw = _wfhw;

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	unsigned int ch = pwm->hwpwm;



	if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {

		unsigned long rate = clk_get_rate(priv->clk);

		u64 ccr_ns;



		/* The result doesn't overflow for rate >= 15259 */

		wf->period_length_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1),

									     NSEC_PER_SEC, rate);



		ccr_ns = stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * wfhw->ccr,

							       NSEC_PER_SEC, rate);



		if (wfhw->ccer & TIM_CCER_CCxP(ch + 1)) {

			wf->duty_length_ns =

				stm32_pwm_mul_u64_u64_div_u64_roundup(((u64)wfhw->psc + 1) * (wfhw->arr + 1 - wfhw->ccr),

								      NSEC_PER_SEC, rate);



			wf->duty_offset_ns = ccr_ns;

		} else {

			wf->duty_length_ns = ccr_ns;

			wf->duty_offset_ns = 0;

		}



		dev_dbg(&chip->dev, "pwm#%u: CCER: %08x, PSC: %08x, ARR: %08x, CCR: %08x @%lu -> %lld/%lld [+%lld]\n",

			pwm->hwpwm, wfhw->ccer, wfhw->psc, wfhw->arr, wfhw->ccr, rate,

			wf->duty_length_ns, wf->period_length_ns, wf->duty_offset_ns);



	} else {

		*wf = (struct pwm_waveform){

			.period_length_ns = 0,

		};

	}



	return 0;

}



static int stm32_pwm_read_waveform(struct pwm_chip *chip,

				     struct pwm_device *pwm,

				     void *_wfhw)

{

	struct stm32_pwm_waveform *wfhw = _wfhw;

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	unsigned int ch = pwm->hwpwm;

	int ret;



	ret = clk_enable(priv->clk);

	if (ret)

		return ret;



	ret = regmap_read(priv->regmap, TIM_CCER, &wfhw->ccer);

	if (ret)

		goto out;



	if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {

		ret = regmap_read(priv->regmap, TIM_PSC, &wfhw->psc);

		if (ret)

			goto out;



		ret = regmap_read(priv->regmap, TIM_ARR, &wfhw->arr);

		if (ret)

			goto out;



		if (wfhw->arr == U32_MAX)

			wfhw->arr -= 1;



		ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &wfhw->ccr);

		if (ret)

			goto out;



		if (wfhw->ccr > wfhw->arr + 1)

			wfhw->ccr = wfhw->arr + 1;

	}



out:

	clk_disable(priv->clk);



	return ret;

}



static int stm32_pwm_write_waveform(struct pwm_chip *chip,

				      struct pwm_device *pwm,

				      const void *_wfhw)

{

	const struct stm32_pwm_waveform *wfhw = _wfhw;

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	unsigned int ch = pwm->hwpwm;

	int ret;



	ret = clk_enable(priv->clk);

	if (ret)

		return ret;



	if (wfhw->ccer & TIM_CCER_CCxE(ch + 1)) {

		u32 ccer, mask;

		unsigned int shift;

		u32 ccmr;



		ret = regmap_read(priv->regmap, TIM_CCER, &ccer);

		if (ret)

			goto out;



		/* If there are other channels enabled, don't update PSC and ARR */

		if (ccer & ~TIM_CCER_CCxE(ch + 1) & TIM_CCER_CCXE) {

			u32 psc, arr;



			ret = regmap_read(priv->regmap, TIM_PSC, &psc);

			if (ret)

				goto out;



			if (psc != wfhw->psc) {

				ret = -EBUSY;

				goto out;

			}



			ret = regmap_read(priv->regmap, TIM_ARR, &arr);

			if (ret)

				goto out;



			if (arr != wfhw->arr) {

				ret = -EBUSY;

				goto out;

			}

		} else {

			ret = regmap_write(priv->regmap, TIM_PSC, wfhw->psc);

			if (ret)

				goto out;



			ret = regmap_write(priv->regmap, TIM_ARR, wfhw->arr);

			if (ret)

				goto out;



			ret = regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);

			if (ret)

				goto out;



		}



		/* set polarity */

		mask = TIM_CCER_CCxP(ch + 1) | TIM_CCER_CCxNP(ch + 1);

		ret = regmap_update_bits(priv->regmap, TIM_CCER, mask, wfhw->ccer);

		if (ret)

			goto out;



		ret = regmap_write(priv->regmap, TIM_CCRx(ch + 1), wfhw->ccr);

		if (ret)

			goto out;



		/* Configure output mode */

		shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;

		ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;

		mask = CCMR_CHANNEL_MASK << shift;



		if (ch < 2)

			ret = regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);

		else

			ret = regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);

		if (ret)

			goto out;



		ret = regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);

		if (ret)

			goto out;



		if (!(ccer & TIM_CCER_CCxE(ch + 1))) {

			mask = TIM_CCER_CCxE(ch + 1) | TIM_CCER_CCxNE(ch + 1);



			ret = clk_enable(priv->clk);

			if (ret)

				goto out;



			ccer = (ccer & ~mask) | (wfhw->ccer & mask);

			regmap_write(priv->regmap, TIM_CCER, ccer);



			/* Make sure that registers are updated */

			regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);



			/* Enable controller */

			regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

		}



	} else {

		/* disable channel */

		u32 mask, ccer;



		mask = TIM_CCER_CCxE(ch + 1);

		if (priv->have_complementary_output)

			mask |= TIM_CCER_CCxNE(ch + 1);



		ret = regmap_read(priv->regmap, TIM_CCER, &ccer);

		if (ret)

			goto out;



		if (ccer & mask) {

			ccer = ccer & ~mask;



			ret = regmap_write(priv->regmap, TIM_CCER, ccer);

			if (ret)

				goto out;



			if (!(ccer & TIM_CCER_CCXE)) {

				/* When all channels are disabled, we can disable the controller */

				ret = regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);

				if (ret)

					goto out;

			}



			clk_disable(priv->clk);

		}

	}



out:

	clk_disable(priv->clk);



	return ret;

}



#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)

#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)

#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
@@ -308,228 +693,13 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, 
	return ret;

}



static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,

			    u64 duty_ns, u64 period_ns)

{

	unsigned long long prd, dty;

	unsigned long long prescaler;

	u32 ccmr, mask, shift;



	/*

	 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so

	 * the calculations here won't overflow.

	 * First we need to find the minimal value for prescaler such that

	 *

	 *        period_ns * clkrate

	 *   ------------------------------ < max_arr + 1

	 *   NSEC_PER_SEC * (prescaler + 1)

	 *

	 * This equation is equivalent to

	 *

	 *        period_ns * clkrate

	 *   ---------------------------- < prescaler + 1

	 *   NSEC_PER_SEC * (max_arr + 1)

	 *

	 * Using integer division and knowing that the right hand side is

	 * integer, this is further equivalent to

	 *

	 *   (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler

	 */



	prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),

					(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));

	if (prescaler > MAX_TIM_PSC)

		return -EINVAL;



	prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),

				  (u64)NSEC_PER_SEC * (prescaler + 1));

	if (!prd)

		return -EINVAL;



	/*

	 * All channels share the same prescaler and counter so when two

	 * channels are active at the same time we can't change them

	 */

	if (active_channels(priv) & ~(1 << ch * 4)) {

		u32 psc, arr;



		regmap_read(priv->regmap, TIM_PSC, &psc);

		regmap_read(priv->regmap, TIM_ARR, &arr);



		if ((psc != prescaler) || (arr != prd - 1))

			return -EBUSY;

	}



	regmap_write(priv->regmap, TIM_PSC, prescaler);

	regmap_write(priv->regmap, TIM_ARR, prd - 1);

	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);



	/* Calculate the duty cycles */

	dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),

				  (u64)NSEC_PER_SEC * (prescaler + 1));



	regmap_write(priv->regmap, TIM_CCRx(ch + 1), dty);



	/* Configure output mode */

	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;

	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;

	mask = CCMR_CHANNEL_MASK << shift;



	if (ch < 2)

		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);

	else

		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);



	regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);



	return 0;

}



static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,

				  enum pwm_polarity polarity)

{

	u32 mask;



	mask = TIM_CCER_CCxP(ch + 1);

	if (priv->have_complementary_output)

		mask |= TIM_CCER_CCxNP(ch + 1);



	regmap_update_bits(priv->regmap, TIM_CCER, mask,

			   polarity == PWM_POLARITY_NORMAL ? 0 : mask);



	return 0;

}



static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)

{

	u32 mask;

	int ret;



	ret = clk_enable(priv->clk);

	if (ret)

		return ret;



	/* Enable channel */

	mask = TIM_CCER_CCxE(ch + 1);

	if (priv->have_complementary_output)

		mask |= TIM_CCER_CCxNE(ch + 1);



	regmap_set_bits(priv->regmap, TIM_CCER, mask);



	/* Make sure that registers are updated */

	regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);



	/* Enable controller */

	regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);



	return 0;

}



static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)

{

	u32 mask;



	/* Disable channel */

	mask = TIM_CCER_CCxE(ch + 1);

	if (priv->have_complementary_output)

		mask |= TIM_CCER_CCxNE(ch + 1);



	regmap_clear_bits(priv->regmap, TIM_CCER, mask);



	/* When all channels are disabled, we can disable the controller */

	if (!active_channels(priv))

		regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);



	clk_disable(priv->clk);

}



static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,

			   const struct pwm_state *state)

{

	bool enabled;

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	int ret;



	enabled = pwm->state.enabled;



	if (!state->enabled) {

		if (enabled)

			stm32_pwm_disable(priv, pwm->hwpwm);

		return 0;

	}



	if (state->polarity != pwm->state.polarity)

		stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);



	ret = stm32_pwm_config(priv, pwm->hwpwm,

			       state->duty_cycle, state->period);

	if (ret)

		return ret;



	if (!enabled && state->enabled)

		ret = stm32_pwm_enable(priv, pwm->hwpwm);



	return ret;

}



static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,

				  const struct pwm_state *state)

{

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	int ret;



	/* protect common prescaler for all active channels */

	mutex_lock(&priv->lock);

	ret = stm32_pwm_apply(chip, pwm, state);

	mutex_unlock(&priv->lock);



	return ret;

}



static int stm32_pwm_get_state(struct pwm_chip *chip,

			       struct pwm_device *pwm, struct pwm_state *state)

{

	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);

	int ch = pwm->hwpwm;

	unsigned long rate;

	u32 ccer, psc, arr, ccr;

	u64 dty, prd;

	int ret;



	mutex_lock(&priv->lock);



	ret = regmap_read(priv->regmap, TIM_CCER, &ccer);

	if (ret)

		goto out;



	state->enabled = ccer & TIM_CCER_CCxE(ch + 1);

	state->polarity = (ccer & TIM_CCER_CCxP(ch + 1)) ?

			  PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;

	ret = regmap_read(priv->regmap, TIM_PSC, &psc);

	if (ret)

		goto out;

	ret = regmap_read(priv->regmap, TIM_ARR, &arr);

	if (ret)

		goto out;

	ret = regmap_read(priv->regmap, TIM_CCRx(ch + 1), &ccr);

	if (ret)

		goto out;



	rate = clk_get_rate(priv->clk);



	prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);

	state->period = DIV_ROUND_UP_ULL(prd, rate);

	dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;

	state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);



out:

	mutex_unlock(&priv->lock);

	return ret;

}



static const struct pwm_ops stm32pwm_ops = {

	.apply = stm32_pwm_apply_locked,

	.get_state = stm32_pwm_get_state,

	.sizeof_wfhw = sizeof(struct stm32_pwm_waveform),

	.round_waveform_tohw = stm32_pwm_round_waveform_tohw,

	.round_waveform_fromhw = stm32_pwm_round_waveform_fromhw,

	.read_waveform = stm32_pwm_read_waveform,

	.write_waveform = stm32_pwm_write_waveform,



	.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,

};

include/linux/pwm.h

+59 −1
Original line number Diff line number Diff line
@@ -49,6 +49,31 @@ enum { 
	PWMF_EXPORTED = 1,

};



/**

 * struct pwm_waveform - description of a PWM waveform

 * @period_length_ns: PWM period

 * @duty_length_ns: PWM duty cycle

 * @duty_offset_ns: offset of the rising edge from the period's start

 *

 * This is a representation of a PWM waveform alternative to struct pwm_state

 * below. It's more expressive than struct pwm_state as it contains a

 * duty_offset_ns and so can represent offsets other than zero (with .polarity =

 * PWM_POLARITY_NORMAL) and period - duty_cycle (.polarity =

 * PWM_POLARITY_INVERSED).

 *

 * Note there is no explicit bool for enabled. A "disabled" PWM is represented

 * by .period_length_ns = 0. Note further that the behaviour of a "disabled" PWM

 * is undefined. Depending on the hardware's capabilities it might drive the

 * active or inactive level, go high-z or even continue to toggle.

 *

 * The unit for all three members is nanoseconds.

 */

struct pwm_waveform {

	u64 period_length_ns;

	u64 duty_length_ns;

	u64 duty_offset_ns;

};



/*

 * struct pwm_state - state of a PWM channel

 * @period: PWM period (in nanoseconds)
@@ -251,6 +276,11 @@ struct pwm_capture { 
 * @request: optional hook for requesting a PWM

 * @free: optional hook for freeing a PWM

 * @capture: capture and report PWM signal

 * @sizeof_wfhw: size (in bytes) of driver specific waveform presentation

 * @round_waveform_tohw: convert a struct pwm_waveform to driver specific presentation

 * @round_waveform_fromhw: convert a driver specific waveform presentation to struct pwm_waveform

 * @read_waveform: read driver specific waveform presentation from hardware

 * @write_waveform: write driver specific waveform presentation to hardware

 * @apply: atomically apply a new PWM config

 * @get_state: get the current PWM state.

 */
@@ -259,6 +289,17 @@ struct pwm_ops { 
	void (*free)(struct pwm_chip *chip, struct pwm_device *pwm);

	int (*capture)(struct pwm_chip *chip, struct pwm_device *pwm,

		       struct pwm_capture *result, unsigned long timeout);



	size_t sizeof_wfhw;

	int (*round_waveform_tohw)(struct pwm_chip *chip, struct pwm_device *pwm,

				   const struct pwm_waveform *wf, void *wfhw);

	int (*round_waveform_fromhw)(struct pwm_chip *chip, struct pwm_device *pwm,

				     const void *wfhw, struct pwm_waveform *wf);

	int (*read_waveform)(struct pwm_chip *chip, struct pwm_device *pwm,

			    void *wfhw);

	int (*write_waveform)(struct pwm_chip *chip, struct pwm_device *pwm,

			      const void *wfhw);



	int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm,

		     const struct pwm_state *state);

	int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -275,6 +316,9 @@ struct pwm_ops { 
 * @of_xlate: request a PWM device given a device tree PWM specifier

 * @atomic: can the driver's ->apply() be called in atomic context

 * @uses_pwmchip_alloc: signals if pwmchip_allow was used to allocate this chip

 * @operational: signals if the chip can be used (or is already deregistered)

 * @nonatomic_lock: mutex for nonatomic chips

 * @atomic_lock: mutex for atomic chips

 * @pwms: array of PWM devices allocated by the framework

 */

struct pwm_chip {
@@ -290,6 +334,16 @@ struct pwm_chip { 


	/* only used internally by the PWM framework */

	bool uses_pwmchip_alloc;

	bool operational;

	union {

		/*

		 * depending on the chip being atomic or not either the mutex or

		 * the spinlock is used. It protects .operational and

		 * synchronizes the callbacks in .ops

		 */

		struct mutex nonatomic_lock;

		spinlock_t atomic_lock;

	};

	struct pwm_device pwms[] __counted_by(npwm);

};
@@ -309,7 +363,11 @@ static inline void pwmchip_set_drvdata(struct pwm_chip *chip, void *data) 
}



#if IS_ENABLED(CONFIG_PWM)

/* PWM user APIs */



/* PWM consumer APIs */

int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf);

int pwm_get_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf);

int pwm_set_waveform_might_sleep(struct pwm_device *pwm, const struct pwm_waveform *wf, bool exact);

int pwm_apply_might_sleep(struct pwm_device *pwm, const struct pwm_state *state);

int pwm_apply_atomic(struct pwm_device *pwm, const struct pwm_state *state);

int pwm_adjust_config(struct pwm_device *pwm);

include/trace/events/pwm.h

+126 −8

File changed.

Preview size limit exceeded, changes collapsed.