Commit ae5bac37 authored by Inochi Amaoto's avatar Inochi Amaoto
Browse files

riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10 

Sophgo SG2044 SRD3-10 board bases on Sophgo SG2044 SoC.
This board includes 5 uart ports, 5 pcie x8 slots, 1 1G Ethernet port,
1 microSD slot.

Add initial device tree of this board with uart support.

Link: https://lore.kernel.org/r/20250413223507.46480-11-inochiama@gmail.com


Signed-off-by: default avatarInochi Amaoto <inochiama@gmail.com>
Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
Signed-off-by: default avatarChen Wang <wangchen20@iscas.ac.cn>
parent 22db96e4

arch/riscv/boot/dts/sophgo/Makefile

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@@ -3,3 +3,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb 
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb

arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi

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File added.

Preview size limit exceeded, changes collapsed.

arch/riscv/boot/dts/sophgo/sg2044-reset.h

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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */

/*

 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>

 */



#ifndef _SG2044_RESET_H

#define _SG2044_RESET_H



#define RST_AP_SYS			0

#define RST_AP_SYS_CORE0		1

#define RST_AP_SYS_CORE1		2

#define RST_AP_SYS_CORE2		3

#define RST_AP_SYS_CORE3		4

#define RST_AP_PIC			5

#define RST_AP_TDT			6

#define RST_RP_PIC_TDT			7

#define RST_HSDMA			8

#define RST_SYSDMA			9

#define RST_EFUSE0			10

#define RST_EFUSE1			11

#define RST_RTC				12

#define RST_TIMER			13

#define RST_WDT				14

#define RST_AHB_ROM0			15

#define RST_AHB_ROM1			16

#define RST_I2C0			17

#define RST_I2C1			18

#define RST_I2C2			19

#define RST_I2C3			20

#define RST_GPIO0			21

#define RST_GPIO1			22

#define RST_GPIO2			23

#define RST_PWM				24

#define RST_AXI_SRAM0			25

#define RST_AXI_SRAM1			26

#define RST_SPIFMC0			27

#define RST_SPIFMC1			28

#define RST_MAILBOX			29

#define RST_ETH0			30

#define RST_EMMC			31

#define RST_SD				32

#define RST_UART0			33

#define RST_UART1			34

#define RST_UART2			35

#define RST_UART3			36

#define RST_SPI0			37

#define RST_SPI1			38

#define RST_MTLI			39

#define RST_DBG_I2C			40

#define RST_C2C0			41

#define RST_C2C1			42

#define RST_C2C2			43

#define RST_C2C3			44

#define RST_CXP				45

#define RST_DDR0			46

#define RST_DDR1			47

#define RST_DDR2			48

#define RST_DDR3			49

#define RST_DDR4			50

#define RST_DDR5			51

#define RST_DDR6			52

#define RST_DDR7			53

#define RST_DDR8			54

#define RST_DDR9			55

#define RST_DDR10			56

#define RST_DDR11			57

#define RST_DDR12			58

#define RST_DDR13			59

#define RST_DDR14			60

#define RST_DDR15			61

#define RST_BAR				62

#define RST_K2K				63

#define RST_CC_SYS_X1Y1			64

#define RST_CC_SYS_X1Y2			65

#define RST_CC_SYS_X1Y3			66

#define RST_CC_SYS_X1Y4			67

#define RST_CC_SYS_X0Y1			68

#define RST_CC_SYS_X0Y2			69

#define RST_CC_SYS_X0Y3			70

#define RST_CC_SYS_X0Y4			71

#define RST_SC_X1Y1			80

#define RST_SC_X1Y2			81

#define RST_SC_X1Y3			82

#define RST_SC_X1Y4			83

#define RST_SC_X0Y1			84

#define RST_SC_X0Y2			85

#define RST_SC_X0Y3			86

#define RST_SC_X0Y4			87

#define RST_RP_CLUSTER_X1Y1_S0		160

#define RST_RP_CLUSTER_X1Y1_S1		161

#define RST_RP_CLUSTER_X1Y2_S0		162

#define RST_RP_CLUSTER_X1Y2_S1		163

#define RST_RP_CLUSTER_X1Y3_S0		164

#define RST_RP_CLUSTER_X1Y3_S1		165

#define RST_RP_CLUSTER_X1Y4_S0		166

#define RST_RP_CLUSTER_X1Y4_S1		167

#define RST_RP_CLUSTER_X0Y1_W0		168

#define RST_RP_CLUSTER_X0Y1_W1		169

#define RST_RP_CLUSTER_X0Y2_W0		170

#define RST_RP_CLUSTER_X0Y2_W1		171

#define RST_RP_CLUSTER_X0Y3_W0		172

#define RST_RP_CLUSTER_X0Y3_W1		173

#define RST_RP_CLUSTER_X0Y4_W0		174

#define RST_RP_CLUSTER_X0Y4_W1		175

#define RST_TPSYS_X1Y1			180

#define RST_TPSYS_X1Y2			181

#define RST_TPSYS_X1Y3			182

#define RST_TPSYS_X1Y4			183

#define RST_TPSYS_X0Y1			184

#define RST_TPSYS_X0Y2			185

#define RST_TPSYS_X0Y3			186

#define RST_TPSYS_X0Y4			187

#define RST_SPACC			188

#define RST_PKA				189

#define RST_SE_TRNG			190

#define RST_SE_DBG			191

#define RST_SE_FAB_FW			192

#define RST_SE_CTRL			193

#define RST_MAILBOX0			194

#define RST_MAILBOX1			195

#define RST_MAILBOX2			196

#define RST_MAILBOX3			197

#define RST_INTC0			198

#define RST_INTC1			199

#define RST_INTC2			200

#define RST_INTC3			201



#endif /* _DT_BINDINGS_SG2044_RESET_H */

arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>

 */



/dts-v1/;



#include "sg2044.dtsi"



/ {

	model = "Sophgo SG2044 SRD3-10";

	compatible = "sophgo,srd3-10", "sophgo,sg2044";



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;

		serial3 = &uart3;

	};



	chosen {

		stdout-path = "serial1:115200n8";

	};

};



&osc {

	clock-frequency = <25000000>;

};



&uart1 {

	status = "okay";

};

arch/riscv/boot/dts/sophgo/sg2044.dtsi

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>

 */



#include <dt-bindings/interrupt-controller/irq.h>



#include "sg2044-cpus.dtsi"

#include "sg2044-reset.h"



/ {

	compatible = "sophgo,sg2044";



	memory@80000000 {

		device_type = "memory";

		reg = <0x00000000 0x80000000 0x00000010 0x00000000>;

	};



	osc: oscillator {

		compatible = "fixed-clock";

		clock-output-names = "osc";

		#clock-cells = <0>;

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		uart0: serial@7030000000 {

			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";

			reg = <0x70 0x30000000 0x0 0x1000>;

			clock-frequency = <500000000>;

			interrupt-parent = <&intc>;

			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			resets = <&rst RST_UART0>;

			status = "disabled";

		};



		uart1: serial@7030001000 {

			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";

			reg = <0x70 0x30001000 0x0 0x1000>;

			clock-frequency = <500000000>;

			interrupt-parent = <&intc>;

			interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			resets = <&rst RST_UART1>;

			status = "disabled";

		};



		uart2: serial@7030002000 {

			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";

			reg = <0x70 0x30002000 0x0 0x1000>;

			clock-frequency = <500000000>;

			interrupt-parent = <&intc>;

			interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			resets = <&rst RST_UART2>;

			status = "disabled";

		};



		uart3: serial@7030003000 {

			compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";

			reg = <0x70 0x30003000 0x0 0x1000>;

			clock-frequency = <500000000>;

			interrupt-parent = <&intc>;

			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;

			reg-io-width = <4>;

			resets = <&rst RST_UART3>;

			status = "disabled";

		};



		rst: reset-controller@7050003000 {

			compatible = "sophgo,sg2044-reset",

				     "sophgo,sg2042-reset";

			reg = <0x70 0x50003000 0x0 0x1000>;

			#reset-cells = <1>;

		};

	};

};