Commit af02ee4f authored by Arun R Murthy's avatar Arun R Murthy Committed by Suraj Kandpal
Browse files

drm/i915/dp: use fsleep instead of usleep_range for LT 



Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range() and
for > 10ms use msleep. flseep() will call the particular API based on
the above condition. (Documentation/timers/timers-howto.rst)
Aux RD Interval value depends on the value read from the dpcd register
which is updated from the sink device, hence use flseep.

Co-developed-by: default avatarSrikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240925034432.1777029-2-arun.r.murthy@intel.com
parent a594f284

drivers/gpu/drm/i915/display/intel_dp_link_training.c

+3 −3
Original line number Diff line number Diff line
@@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 


	voltage_tries = 1;

	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {

		usleep_range(delay_us, 2 * delay_us);

		fsleep(delay_us);



		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

						     link_status) < 0) {
@@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 
	}



	for (tries = 0; tries < 5; tries++) {

		usleep_range(delay_us, 2 * delay_us);

		fsleep(delay_us);



		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,

						     link_status) < 0) {
@@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 
	deadline = jiffies + msecs_to_jiffies_timeout(400);



	for (try = 0; try < max_tries; try++) {

		usleep_range(delay_us, 2 * delay_us);

		fsleep(delay_us);



		/*

		 * The delay may get updated. The transmitter shall read the