Commit af05917c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.11' of... 

Merge tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Add reset controller support to audiomix block control
 - Add CLK_SET_RATE_PARENT flag to all audiomix clocks and to
   i.MX7D lcdif_pixel_src clock
 - Fix parent clocks for earc_phy and audpll on i.MX8MP
 - Fix default parents for enet[12]_ref_sel on i.MX6UL
 - Add ops in composite 8M and 93 that allow no-op on disable
 - Add check for PCC present bit on composite 7ULP register
 - Fix fractional part for fracn-gppll on prepare
 - Fix clock tree update for TF-A managed clocks on i.MX8M
 - Drop CLK_SET_PARENT_GATE for DRAM mux on i.MX7D
 - Add the SAI7 IPG clock for i.MX8MN
 - Mark the 'nand_usdhc_bus' clock as non-critical on i.MX8MM
 - Add LVDS bypass clocks on i.MX8QXP
 - Add muxes for MIPI and PHY ref clocks
 - Reorder dc0_bypass0_clk, lcd_pxl and dc1_disp clocks on i.MX8QXP
 - Add 1039.5MHz and 800MHz rates to fracn-gppll table
 - Add CLK_SET_RATE_PARENT for media_disp pixel clocks on i.MX8QXP
 - Add some module descriptions to the i.MX generic and the
   i.MXRT1050 driver.
 - Fix return value for bypass for composite 7ULP

* tag 'clk-imx-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (22 commits)
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  clk: imx: composite-93: keep root clock on when mcore enabled
  clk: imx: composite-8m: Enable gate clk with mcore_booted
  clk: imx: imx6ul: fix default parent for enet*_ref_sel
  clk: imx: clk-audiomix: Correct parent clock for earc_phy and audpll
  clk: imx: clk-audiomix: Add CLK_SET_RATE_PARENT flags for clocks
  ...
parents 1613e604 466da3d2

Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

+3 −0
Original line number Diff line number Diff line
@@ -44,6 +44,9 @@ properties: 
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h

      for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

drivers/clk/imx/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ config CLK_IMX8MP 
	tristate "IMX8MP CCM Clock Driver"

	depends on ARCH_MXC || COMPILE_TEST

	select MXC_CLK

	select AUXILIARY_BUS if RESET_CONTROLLER

	help

	    Build the driver for i.MX8MP CCM Clock Driver

drivers/clk/imx/clk-composite-7ulp.c

+7 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "../clk-fractional-divider.h"

#include "clk.h"



#define PCG_PR_MASK		BIT(31)

#define PCG_PCS_SHIFT	24

#define PCG_PCS_MASK	0x7

#define PCG_CGC_SHIFT	30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, 
	struct clk_hw *hw;

	u32 val;



	val = readl(reg);

	if (!(val & PCG_PR_MASK)) {

		pr_info("PCC PR is 0 for clk:%s, bypass\n", name);

		return NULL;

	}



	if (mux_present) {

		mux = kzalloc(sizeof(*mux), GFP_KERNEL);

		if (!mux)

drivers/clk/imx/clk-composite-8m.c

+42 −11
Original line number Diff line number Diff line
@@ -204,6 +204,34 @@ static const struct clk_ops imx8m_clk_composite_mux_ops = { 
	.determine_rate = imx8m_clk_composite_mux_determine_rate,

};



static int imx8m_clk_composite_gate_enable(struct clk_hw *hw)

{

	struct clk_gate *gate = to_clk_gate(hw);

	unsigned long flags;

	u32 val;



	spin_lock_irqsave(gate->lock, flags);



	val = readl(gate->reg);

	val |= BIT(gate->bit_idx);

	writel(val, gate->reg);



	spin_unlock_irqrestore(gate->lock, flags);



	return 0;

}



static void imx8m_clk_composite_gate_disable(struct clk_hw *hw)

{

	/* composite clk requires the disable hook */

}



static const struct clk_ops imx8m_clk_composite_gate_ops = {

	.enable = imx8m_clk_composite_gate_enable,

	.disable = imx8m_clk_composite_gate_disable,

	.is_enabled = clk_gate_is_enabled,

};



struct clk_hw *__imx8m_clk_hw_composite(const char *name,

					const char * const *parent_names,

					int num_parents, void __iomem *reg,
@@ -217,6 +245,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
	struct clk_mux *mux;

	const struct clk_ops *divider_ops;

	const struct clk_ops *mux_ops;

	const struct clk_ops *gate_ops;



	mux = kzalloc(sizeof(*mux), GFP_KERNEL);

	if (!mux)
@@ -257,7 +286,6 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
	div->flags = CLK_DIVIDER_ROUND_CLOSEST;



	/* skip registering the gate ops if M4 is enabled */

	if (!mcore_booted) {

	gate = kzalloc(sizeof(*gate), GFP_KERNEL);

	if (!gate)

		goto free_div;
@@ -266,11 +294,14 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, 
	gate->reg = reg;

	gate->bit_idx = PCG_CGC_SHIFT;

	gate->lock = &imx_ccm_lock;

	}

	if (!mcore_booted)

		gate_ops = &clk_gate_ops;

	else

		gate_ops = &imx8m_clk_composite_gate_ops;



	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

			mux_hw, mux_ops, div_hw,

			divider_ops, gate_hw, &clk_gate_ops, flags);

			divider_ops, gate_hw, gate_ops, flags);

	if (IS_ERR(hw))

		goto free_gate;

drivers/clk/imx/clk-composite-93.c

+8 −7
Original line number Diff line number Diff line
@@ -76,6 +76,13 @@ static int imx93_clk_composite_gate_enable(struct clk_hw *hw) 


static void imx93_clk_composite_gate_disable(struct clk_hw *hw)

{

	/*

	 * Skip disable the root clock gate if mcore enabled.

	 * The root clock may be used by the mcore.

	 */

	if (mcore_booted)

		return;



	imx93_clk_composite_gate_endisable(hw, 0);

}
@@ -222,7 +229,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p 
		hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

					       mux_hw, &clk_mux_ro_ops, div_hw,

					       &clk_divider_ro_ops, NULL, NULL, flags);

	} else if (!mcore_booted) {

	} else {

		gate = kzalloc(sizeof(*gate), GFP_KERNEL);

		if (!gate)

			goto fail;
@@ -238,12 +245,6 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p 
					       &imx93_clk_composite_divider_ops, gate_hw,

					       &imx93_clk_composite_gate_ops,

					       flags | CLK_SET_RATE_NO_REPARENT);

	} else {

		hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,

					       mux_hw, &imx93_clk_composite_mux_ops, div_hw,

					       &imx93_clk_composite_divider_ops, NULL,

					       &imx93_clk_composite_gate_ops,

					       flags | CLK_SET_RATE_NO_REPARENT);

	}



	if (IS_ERR(hw))