Commit af2d78dc authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: Add FGT descriptors for FEAT_FGT2 



Bulk addition of all the FGT2 traps reported with EC == 0x18,
as described in the 2025-03 JSON drop.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent f654e9e4

arch/arm64/kvm/emulate-nested.c

+83 −0
Original line number Diff line number Diff line
@@ -1388,6 +1388,24 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 
	SR_FGT(SYS_AIDR_EL1, 		HFGRTR, AIDR_EL1, 1),

	SR_FGT(SYS_AFSR1_EL1, 		HFGRTR, AFSR1_EL1, 1),

	SR_FGT(SYS_AFSR0_EL1, 		HFGRTR, AFSR0_EL1, 1),



	/* HFGRTR2_EL2, HFGWTR2_EL2 */

	SR_FGT(SYS_ACTLRALIAS_EL1,	HFGRTR2, nACTLRALIAS_EL1, 0),

	SR_FGT(SYS_ACTLRMASK_EL1,	HFGRTR2, nACTLRMASK_EL1, 0),

	SR_FGT(SYS_CPACRALIAS_EL1,	HFGRTR2, nCPACRALIAS_EL1, 0),

	SR_FGT(SYS_CPACRMASK_EL1,	HFGRTR2, nCPACRMASK_EL1, 0),

	SR_FGT(SYS_PFAR_EL1,		HFGRTR2, nPFAR_EL1, 0),

	SR_FGT(SYS_RCWSMASK_EL1,	HFGRTR2, nRCWSMASK_EL1, 0),

	SR_FGT(SYS_SCTLR2ALIAS_EL1,	HFGRTR2, nSCTLRALIAS2_EL1, 0),

	SR_FGT(SYS_SCTLR2MASK_EL1,	HFGRTR2, nSCTLR2MASK_EL1, 0),

	SR_FGT(SYS_SCTLRALIAS_EL1,	HFGRTR2, nSCTLRALIAS_EL1, 0),

	SR_FGT(SYS_SCTLRMASK_EL1,	HFGRTR2, nSCTLRMASK_EL1, 0),

	SR_FGT(SYS_TCR2ALIAS_EL1,	HFGRTR2, nTCR2ALIAS_EL1, 0),

	SR_FGT(SYS_TCR2MASK_EL1,	HFGRTR2, nTCR2MASK_EL1, 0),

	SR_FGT(SYS_TCRALIAS_EL1,	HFGRTR2, nTCRALIAS_EL1, 0),

	SR_FGT(SYS_TCRMASK_EL1,		HFGRTR2, nTCRMASK_EL1, 0),

	SR_FGT(SYS_ERXGSR_EL1,		HFGRTR2, nERXGSR_EL1, 0),



	/* HFGITR_EL2 */

	SR_FGT(OP_AT_S1E1A, 		HFGITR, ATS1E1A, 1),

	SR_FGT(OP_COSP_RCTX, 		HFGITR, COSPRCTX, 1),
@@ -1497,6 +1515,11 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 
	SR_FGT(SYS_IC_IVAU, 		HFGITR, ICIVAU, 1),

	SR_FGT(SYS_IC_IALLU, 		HFGITR, ICIALLU, 1),

	SR_FGT(SYS_IC_IALLUIS, 		HFGITR, ICIALLUIS, 1),



	/* HFGITR2_EL2 */

	SR_FGT(SYS_DC_CIGDVAPS,		HFGITR2, nDCCIVAPS, 0),

	SR_FGT(SYS_DC_CIVAPS,		HFGITR2, nDCCIVAPS, 0),



	/* HDFGRTR_EL2 */

	SR_FGT(SYS_PMBIDR_EL1, 		HDFGRTR, PMBIDR_EL1, 1),

	SR_FGT(SYS_PMSNEVFR_EL1, 	HDFGRTR, nPMSNEVFR_EL1, 0),
@@ -1889,6 +1912,59 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 
	SR_FGT(SYS_DBGBCRn_EL1(13), 	HDFGRTR, DBGBCRn_EL1, 1),

	SR_FGT(SYS_DBGBCRn_EL1(14), 	HDFGRTR, DBGBCRn_EL1, 1),

	SR_FGT(SYS_DBGBCRn_EL1(15), 	HDFGRTR, DBGBCRn_EL1, 1),



	/* HDFGRTR2_EL2 */

	SR_FGT(SYS_MDSELR_EL1,		HDFGRTR2, nMDSELR_EL1, 0),

	SR_FGT(SYS_MDSTEPOP_EL1,	HDFGRTR2, nMDSTEPOP_EL1, 0),

	SR_FGT(SYS_PMCCNTSVR_EL1,	HDFGRTR2, nPMSSDATA, 0),

	SR_FGT_RANGE(SYS_PMEVCNTSVRn_EL1(0),

		     SYS_PMEVCNTSVRn_EL1(30),

		     HDFGRTR2, nPMSSDATA, 0),

	SR_FGT(SYS_PMICNTSVR_EL1,	HDFGRTR2, nPMSSDATA, 0),

	SR_FGT(SYS_PMECR_EL1,		HDFGRTR2, nPMECR_EL1, 0),

	SR_FGT(SYS_PMIAR_EL1,		HDFGRTR2, nPMIAR_EL1, 0),

	SR_FGT(SYS_PMICFILTR_EL0,	HDFGRTR2, nPMICFILTR_EL0, 0),

	SR_FGT(SYS_PMICNTR_EL0,		HDFGRTR2, nPMICNTR_EL0, 0),

	SR_FGT(SYS_PMSSCR_EL1,		HDFGRTR2, nPMSSCR_EL1, 0),

	SR_FGT(SYS_PMUACR_EL1,		HDFGRTR2, nPMUACR_EL1, 0),

	SR_FGT(SYS_SPMACCESSR_EL1,	HDFGRTR2, nSPMACCESSR_EL1, 0),

	SR_FGT(SYS_SPMCFGR_EL1,		HDFGRTR2, nSPMID, 0),

	SR_FGT(SYS_SPMDEVARCH_EL1,	HDFGRTR2, nSPMID, 0),

	SR_FGT(SYS_SPMCGCRn_EL1(0),	HDFGRTR2, nSPMID, 0),

	SR_FGT(SYS_SPMCGCRn_EL1(1),	HDFGRTR2, nSPMID, 0),

	SR_FGT(SYS_SPMIIDR_EL1,		HDFGRTR2, nSPMID, 0),

	SR_FGT(SYS_SPMCNTENCLR_EL0,	HDFGRTR2, nSPMCNTEN, 0),

	SR_FGT(SYS_SPMCNTENSET_EL0,	HDFGRTR2, nSPMCNTEN, 0),

	SR_FGT(SYS_SPMCR_EL0,		HDFGRTR2, nSPMCR_EL0, 0),

	SR_FGT(SYS_SPMDEVAFF_EL1,	HDFGRTR2, nSPMDEVAFF_EL1, 0),

	/*

	 * We have up to 64 of these registers in ranges of 16, banked via

	 * SPMSELR_EL0.BANK. We're only concerned with the accessors here,

	 * not the architectural registers.

	 */

	SR_FGT_RANGE(SYS_SPMEVCNTRn_EL0(0),

		     SYS_SPMEVCNTRn_EL0(15),

		     HDFGRTR2, nSPMEVCNTRn_EL0, 0),

	SR_FGT_RANGE(SYS_SPMEVFILT2Rn_EL0(0),

		     SYS_SPMEVFILT2Rn_EL0(15),

		     HDFGRTR2, nSPMEVTYPERn_EL0, 0),

	SR_FGT_RANGE(SYS_SPMEVFILTRn_EL0(0),

		     SYS_SPMEVFILTRn_EL0(15),

		     HDFGRTR2, nSPMEVTYPERn_EL0, 0),

	SR_FGT_RANGE(SYS_SPMEVTYPERn_EL0(0),

		     SYS_SPMEVTYPERn_EL0(15),

		     HDFGRTR2, nSPMEVTYPERn_EL0, 0),

	SR_FGT(SYS_SPMINTENCLR_EL1,	HDFGRTR2, nSPMINTEN, 0),

	SR_FGT(SYS_SPMINTENSET_EL1,	HDFGRTR2, nSPMINTEN, 0),

	SR_FGT(SYS_SPMOVSCLR_EL0,	HDFGRTR2, nSPMOVS, 0),

	SR_FGT(SYS_SPMOVSSET_EL0,	HDFGRTR2, nSPMOVS, 0),

	SR_FGT(SYS_SPMSCR_EL1,		HDFGRTR2, nSPMSCR_EL1, 0),

	SR_FGT(SYS_SPMSELR_EL0,		HDFGRTR2, nSPMSELR_EL0, 0),

	SR_FGT(SYS_TRCITECR_EL1,	HDFGRTR2, nTRCITECR_EL1, 0),

	SR_FGT(SYS_PMBMAR_EL1,		HDFGRTR2, nPMBMAR_EL1, 0),

	SR_FGT(SYS_PMSDSFR_EL1,		HDFGRTR2, nPMSDSFR_EL1, 0),

	SR_FGT(SYS_TRBMPAM_EL1,		HDFGRTR2, nTRBMPAM_EL1, 0),



	/*

	 * HDFGWTR_EL2

	 *
@@ -1899,12 +1975,19 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { 
	 * read-side mappings, and only the write-side mappings that

	 * differ from the read side, and the trap handler will pick

	 * the correct shadow register based on the access type.

	 *

	 * Same model applies to the FEAT_FGT2 registers.

	 */

	SR_FGT(SYS_TRFCR_EL1,		HDFGWTR, TRFCR_EL1, 1),

	SR_FGT(SYS_TRCOSLAR,		HDFGWTR, TRCOSLAR, 1),

	SR_FGT(SYS_PMCR_EL0,		HDFGWTR, PMCR_EL0, 1),

	SR_FGT(SYS_PMSWINC_EL0,		HDFGWTR, PMSWINC_EL0, 1),

	SR_FGT(SYS_OSLAR_EL1,		HDFGWTR, OSLAR_EL1, 1),



	/* HDFGWTR2_EL2 */

	SR_FGT(SYS_PMZR_EL0,		HDFGWTR2, nPMZR_EL0, 0),

	SR_FGT(SYS_SPMZR_EL0,		HDFGWTR2, nSPMEVCNTRn_EL0, 0),



	/*

	 * HAFGRTR_EL2

	 */