Commit af326375 authored by Vasant Hegde's avatar Vasant Hegde Committed by Joerg Roedel
Browse files

iommu/amd: Rename iommu_flush_all_caches() -> amd_iommu_flush_all_caches()



Rename function inline with driver naming convention.

No functional changes.

Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Reviewed-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20231122090215.6191-2-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 57cdb720
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+5 −0
Original line number Diff line number Diff line
@@ -53,6 +53,11 @@ int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev);
void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev);

int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
/*
 * This function flushes all internal caches of
 * the IOMMU used by this driver.
 */
void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
void amd_iommu_domain_update(struct protection_domain *domain);
void amd_iommu_domain_flush_complete(struct protection_domain *domain);
+0 −6
Original line number Diff line number Diff line
@@ -902,12 +902,6 @@ extern int amd_iommu_max_glx_val;
extern u64 amd_iommu_efr;
extern u64 amd_iommu_efr2;

/*
 * This function flushes all internal caches of
 * the IOMMU used by this driver.
 */
void iommu_flush_all_caches(struct amd_iommu *iommu);

static inline int get_ioapic_devid(int id)
{
	struct devid_map *entry;
+4 −4
Original line number Diff line number Diff line
@@ -2223,7 +2223,7 @@ static int __init amd_iommu_init_pci(void)
		init_device_table_dma(pci_seg);

	for_each_iommu(iommu)
		iommu_flush_all_caches(iommu);
		amd_iommu_flush_all_caches(iommu);

	print_iommu_info();

@@ -2773,7 +2773,7 @@ static void early_enable_iommu(struct amd_iommu *iommu)
	iommu_enable_xt(iommu);
	iommu_enable_irtcachedis(iommu);
	iommu_enable(iommu);
	iommu_flush_all_caches(iommu);
	amd_iommu_flush_all_caches(iommu);
}

/*
@@ -2829,7 +2829,7 @@ static void early_enable_iommus(void)
			iommu_enable_xt(iommu);
			iommu_enable_irtcachedis(iommu);
			iommu_set_device_table(iommu);
			iommu_flush_all_caches(iommu);
			amd_iommu_flush_all_caches(iommu);
		}
	}
}
@@ -3293,7 +3293,7 @@ static int __init state_next(void)
				uninit_device_table_dma(pci_seg);

			for_each_iommu(iommu)
				iommu_flush_all_caches(iommu);
				amd_iommu_flush_all_caches(iommu);
		}
	}
	return ret;
+1 −1
Original line number Diff line number Diff line
@@ -1392,7 +1392,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
	iommu_completion_wait(iommu);
}

void iommu_flush_all_caches(struct amd_iommu *iommu)
void amd_iommu_flush_all_caches(struct amd_iommu *iommu)
{
	if (check_feature(FEATURE_IA)) {
		amd_iommu_flush_all(iommu);