Commit afd0406b authored by Dong Aisheng's avatar Dong Aisheng Committed by Abel Vesa
Browse files

clk: imx8qm: add clock valid resource checking 



Add imx8qm clock valid resource checking mechanism

Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
parent 5964012c

drivers/clk/imx/Makefile

+1 −1
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@@ -28,7 +28,7 @@ obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o 


obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o

clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \

				     clk-imx8qxp-rsrc.o

				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o

clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o



obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o

drivers/clk/imx/clk-imx8qm-rsrc.c

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+116 −0
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// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019-2021 NXP

 *	Dong Aisheng <aisheng.dong@nxp.com>

 */



#include <dt-bindings/firmware/imx/rsrc.h>



#include "clk-scu.h"



/* Keep sorted in the ascending order */

static const u32 imx8qm_clk_scu_rsrc_table[] = {

	IMX_SC_R_A53,

	IMX_SC_R_A72,

	IMX_SC_R_DC_0_VIDEO0,

	IMX_SC_R_DC_0_VIDEO1,

	IMX_SC_R_DC_0,

	IMX_SC_R_DC_0_PLL_0,

	IMX_SC_R_DC_0_PLL_1,

	IMX_SC_R_DC_1_VIDEO0,

	IMX_SC_R_DC_1_VIDEO1,

	IMX_SC_R_DC_1,

	IMX_SC_R_DC_1_PLL_0,

	IMX_SC_R_DC_1_PLL_1,

	IMX_SC_R_SPI_0,

	IMX_SC_R_SPI_1,

	IMX_SC_R_SPI_2,

	IMX_SC_R_SPI_3,

	IMX_SC_R_UART_0,

	IMX_SC_R_UART_1,

	IMX_SC_R_UART_2,

	IMX_SC_R_UART_3,

	IMX_SC_R_UART_4,

	IMX_SC_R_EMVSIM_0,

	IMX_SC_R_EMVSIM_1,

	IMX_SC_R_I2C_0,

	IMX_SC_R_I2C_1,

	IMX_SC_R_I2C_2,

	IMX_SC_R_I2C_3,

	IMX_SC_R_I2C_4,

	IMX_SC_R_ADC_0,

	IMX_SC_R_ADC_1,

	IMX_SC_R_FTM_0,

	IMX_SC_R_FTM_1,

	IMX_SC_R_CAN_0,

	IMX_SC_R_GPU_0_PID0,

	IMX_SC_R_GPU_1_PID0,

	IMX_SC_R_PWM_0,

	IMX_SC_R_PWM_1,

	IMX_SC_R_PWM_2,

	IMX_SC_R_PWM_3,

	IMX_SC_R_PWM_4,

	IMX_SC_R_PWM_5,

	IMX_SC_R_PWM_6,

	IMX_SC_R_PWM_7,

	IMX_SC_R_GPT_0,

	IMX_SC_R_GPT_1,

	IMX_SC_R_GPT_2,

	IMX_SC_R_GPT_3,

	IMX_SC_R_GPT_4,

	IMX_SC_R_FSPI_0,

	IMX_SC_R_FSPI_1,

	IMX_SC_R_SDHC_0,

	IMX_SC_R_SDHC_1,

	IMX_SC_R_SDHC_2,

	IMX_SC_R_ENET_0,

	IMX_SC_R_ENET_1,

	IMX_SC_R_MLB_0,

	IMX_SC_R_USB_2,

	IMX_SC_R_NAND,

	IMX_SC_R_LVDS_0,

	IMX_SC_R_LVDS_0_PWM_0,

	IMX_SC_R_LVDS_0_I2C_0,

	IMX_SC_R_LVDS_0_I2C_1,

	IMX_SC_R_LVDS_1,

	IMX_SC_R_LVDS_1_PWM_0,

	IMX_SC_R_LVDS_1_I2C_0,

	IMX_SC_R_LVDS_1_I2C_1,

	IMX_SC_R_M4_0_I2C,

	IMX_SC_R_M4_1_I2C,

	IMX_SC_R_AUDIO_PLL_0,

	IMX_SC_R_VPU_UART,

	IMX_SC_R_VPUCORE,

	IMX_SC_R_MIPI_0,

	IMX_SC_R_MIPI_0_PWM_0,

	IMX_SC_R_MIPI_0_I2C_0,

	IMX_SC_R_MIPI_0_I2C_1,

	IMX_SC_R_MIPI_1,

	IMX_SC_R_MIPI_1_PWM_0,

	IMX_SC_R_MIPI_1_I2C_0,

	IMX_SC_R_MIPI_1_I2C_1,

	IMX_SC_R_CSI_0,

	IMX_SC_R_CSI_0_PWM_0,

	IMX_SC_R_CSI_0_I2C_0,

	IMX_SC_R_CSI_1,

	IMX_SC_R_CSI_1_PWM_0,

	IMX_SC_R_CSI_1_I2C_0,

	IMX_SC_R_HDMI,

	IMX_SC_R_HDMI_I2S,

	IMX_SC_R_HDMI_I2C_0,

	IMX_SC_R_HDMI_PLL_0,

	IMX_SC_R_HDMI_RX,

	IMX_SC_R_HDMI_RX_BYPASS,

	IMX_SC_R_HDMI_RX_I2C_0,

	IMX_SC_R_AUDIO_PLL_1,

	IMX_SC_R_AUDIO_CLK_0,

	IMX_SC_R_AUDIO_CLK_1,

	IMX_SC_R_HDMI_RX_PWM_0,

	IMX_SC_R_HDMI_PLL_1,

	IMX_SC_R_VPU,

};



const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {

	.rsrc = imx8qm_clk_scu_rsrc_table,

	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),

};

drivers/clk/imx/clk-imx8qxp.c

+1 −0
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@@ -134,6 +134,7 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) 
static const struct of_device_id imx8qxp_match[] = {

	{ .compatible = "fsl,scu-clk", },

	{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },

	{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },

	{ /* sentinel */ }

};

drivers/clk/imx/clk-scu.h

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@@ -22,6 +22,7 @@ struct imx_clk_scu_rsrc_table { 
extern struct list_head imx_scu_clks[];

extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;

extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;

extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;



int imx_clk_scu_init(struct device_node *np,

		     const struct imx_clk_scu_rsrc_table *data);