Commit b0830e7e authored by Joy Zou's avatar Joy Zou Committed by Shawn Guo
Browse files

arm64: dts: imx91: add i.MX91 dtsi support 



The i.MX 91 family features an Arm Cortex-A55 running at up to 1.4GHz,
support for modern LPDDR4 memory to enable platform longevity, along
with a rich set of peripherals targeting medical, industrial and
consumer IoT market segments.

The mainly difference between i.MX91 and i.MX93 is as follows:
- i.MX91 removed some clocks and modified the names of some clocks.
- i.MX91 only has one A core.
- i.MX91 has different pinmux.

Tested-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarJoy Zou <joy.zou@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 80ae4194

arch/arm64/boot/dts/freescale/imx91-pinfunc.h

0 → 100644
+770 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm64/boot/dts/freescale/imx91.dtsi

0 → 100644
+71 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2025 NXP

 */



#include "imx91-pinfunc.h"

#include "imx91_93_common.dtsi"



&clk {

	compatible = "fsl,imx91-ccm";

};



&ddr_pmu {

	compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";

};



&eqos {

	clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,

		 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,

		 <&clk IMX91_CLK_ENET_TIMER>,

		 <&clk IMX91_CLK_ENET1_QOS_TSN>,

		 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;

	assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,

			  <&clk IMX91_CLK_ENET1_QOS_TSN>;

	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,

				 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;

	assigned-clock-rates = <100000000>, <250000000>;

};



&fec {

	clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,

		 <&clk IMX91_CLK_ENET2_REGULAR_GATE>,

		 <&clk IMX91_CLK_ENET_TIMER>,

		 <&clk IMX91_CLK_ENET2_REGULAR>,

		 <&clk IMX93_CLK_DUMMY>;

	assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,

			  <&clk IMX91_CLK_ENET2_REGULAR>;

	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,

				 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;

	assigned-clock-rates = <100000000>, <250000000>;

};



&i3c1 {

	clocks = <&clk IMX93_CLK_BUS_AON>,

		 <&clk IMX93_CLK_I3C1_GATE>,

		 <&clk IMX93_CLK_DUMMY>;

};



&i3c2 {

	clocks = <&clk IMX93_CLK_BUS_WAKEUP>,

		 <&clk IMX93_CLK_I3C2_GATE>,

		 <&clk IMX93_CLK_DUMMY>;

};



&iomuxc {

	compatible = "fsl,imx91-iomuxc";

};



&media_blk_ctrl {

	compatible = "fsl,imx91-media-blk-ctrl", "syscon";

	clocks = <&clk IMX93_CLK_MEDIA_APB>,

		 <&clk IMX93_CLK_MEDIA_AXI>,

		 <&clk IMX93_CLK_NIC_MEDIA_GATE>,

		 <&clk IMX93_CLK_MEDIA_DISP_PIX>,

		 <&clk IMX93_CLK_CAM_PIX>,

		 <&clk IMX93_CLK_LCDIF_GATE>,

		 <&clk IMX93_CLK_ISI_GATE>,

		 <&clk IMX93_CLK_MIPI_CSI_GATE>;

	clock-names = "apb", "axi", "nic", "disp", "cam",

		      "lcdif", "isi", "csi";

};

arch/arm64/boot/dts/freescale/imx91_93_common.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -1178,7 +1178,7 @@ memory-controller@4e300000 { 
			little-endian;

		};



		ddr-pmu@4e300dc0 {

		ddr_pmu: ddr-pmu@4e300dc0 {

			compatible = "fsl,imx93-ddr-pmu";

			reg = <0x4e300dc0 0x200>;

			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;