Commit b0ad56ce authored by Radhakrishna Sripada's avatar Radhakrishna Sripada Committed by Matt Roper
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drm/i915/xe3lpd: Add cdclk changes 



Xe3_LPD has new max cdclk of 691200 which requires reusing the lnl table
and modify/add higher frequencies. Updating the max cdclk supported by
the platform and voltage_level determination is also updated.

There are minor changes in cdclk programming sequence compared to lnl,
where programming cd2x divider needs to be skipped. This is already handled
by the calculations in existing code.

v2: update tables
v3: xe3lpd doesn't supply the power control unit the voltage index

Bspec: 68861, 68863, 68864
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241018200311.67324-3-matthew.s.atwood@intel.com
parent 1901e9a4

drivers/gpu/drm/i915/display/intel_cdclk.c

+57 −2
Original line number Diff line number Diff line
@@ -1468,6 +1468,39 @@ static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 
	{}

};



static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {

	{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },

	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },

	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },

	{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },

	{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },

	{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },

	{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },

	{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },

	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },

	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },

	{}

};



static const int cdclk_squash_len = 16;



static int cdclk_squash_divider(u16 waveform)
@@ -1594,6 +1627,16 @@ static u8 rplu_calc_voltage_level(int cdclk) 
				  rplu_voltage_level_max_cdclk);

}



static u8 xe3lpd_calc_voltage_level(int cdclk)

{

	/*

	 * Starting with xe3lpd power controller does not need the voltage

	 * index when doing the modeset update. This function is best left

	 * defined but returning 0 to the mask.

	 */

	return 0;

}



static void icl_readout_refclk(struct intel_display *display,

			       struct intel_cdclk_config *cdclk_config)

{
@@ -3437,7 +3480,9 @@ void intel_update_max_cdclk(struct intel_display *display) 
{

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

	if (DISPLAY_VER(display) >= 30) {

		display->cdclk.max_cdclk_freq = 691200;

	} else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {

		if (display->cdclk.hw.ref == 24000)

			display->cdclk.max_cdclk_freq = 552000;

		else
@@ -3650,6 +3695,13 @@ void intel_cdclk_debugfs_register(struct intel_display *display) 
			    display, &i915_cdclk_info_fops);

}



static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,

	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,

	.calc_voltage_level = xe3lpd_calc_voltage_level,

};



static const struct intel_cdclk_funcs rplu_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,
@@ -3794,7 +3846,10 @@ void intel_init_cdclk_hooks(struct intel_display *display) 
{

	struct drm_i915_private *dev_priv = to_i915(display->drm);



	if (DISPLAY_VER(display) >= 20) {

	if (DISPLAY_VER(display) >= 30) {

		display->funcs.cdclk = &xe3lpd_cdclk_funcs;

		display->cdclk.table = xe3lpd_cdclk_table;

	} else if (DISPLAY_VER(display) >= 20) {

		display->funcs.cdclk = &rplu_cdclk_funcs;

		display->cdclk.table = xe2lpd_cdclk_table;

	} else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) {