Commit b121e788 authored by Biju Das's avatar Biju Das Committed by Daniel Lezcano
Browse files

dt-bindings: timer: renesas,rz-mtu3: Improve documentation 



Fix the documentation issues pointed by Pavel while backporting
it to 6.1.y-cip.
 - Replace '32- bit'->'32-bit'
 - Consistently remove '.' at the end of line for the specifications
 - Replace '          (excluding MTU8)'-> '(excluding MTU8)'

Reported-by: default avatarPavel Machek <pavel@denx.de>
Closes: https://lore.kernel.org/all/ZH79%2FUjgYg+0Ruiu@duo.ucw.cz


Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20230727081848.100834-3-biju.das.jz@bp.renesas.com
parent b7a8f1f7

Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml

+14 −14
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ maintainers: 
description: |

  This hardware block consists of eight 16-bit timer channels and one

  32-bit timer channel. It supports the following specifications:

    - Pulse input/output: 28 lines max.

    - Pulse input/output: 28 lines max

    - Pulse input 3 lines

    - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks

      for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
@@ -23,11 +23,11 @@ description: | 
        - Input capture function (noise filter setting available)

        - Counter-clearing operation

        - Simultaneous writing to multiple timer counters (TCNT)

          (excluding MTU8).

          (excluding MTU8)

        - Simultaneous clearing on compare match or input capture

          (excluding MTU8).

          (excluding MTU8)

        - Simultaneous input and output to registers in synchronization with

          counter operations           (excluding MTU8).

          counter operations (excluding MTU8)

        - Up to 12-phase PWM output in combination with synchronous operation

          (excluding MTU8)

    - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
@@ -40,26 +40,26 @@ description: | 
    - [MTU3, MTU4, MTU6, and MTU7]

        - Through interlocked operation of MTU3/4 and MTU6/7, the positive and

          negative signals in six phases (12 phases in total) can be output in

          complementary PWM and reset-synchronized PWM operation.

          complementary PWM and reset-synchronized PWM operation

        - In complementary PWM mode, values can be transferred from buffer

          registers to temporary registers at crests and troughs of the timer-

          counter values or when the buffer registers (TGRD registers in MTU4

          and MTU7) are written to.

        - Double-buffering selectable in complementary PWM mode.

          and MTU7) are written to

        - Double-buffering selectable in complementary PWM mode

    - [MTU3 and MTU4]

        - Through interlocking with MTU0, a mode for driving AC synchronous

          motors (brushless DC motors) by using complementary PWM output and

          reset-synchronized PWM output is settable and allows the selection

          of two types of waveform output (chopping or level).

          of two types of waveform output (chopping or level)

    - [MTU5]

        - Capable of operation as a dead-time compensation counter.

        - Capable of operation as a dead-time compensation counter

    - [MTU0/MTU5, MTU1, MTU2, and MTU8]

        - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and

          through interlocked operation with MTU0/MTU5 and MTU8.

          through interlocked operation with MTU0/MTU5 and MTU8

    - Interrupt-skipping function

        - In complementary PWM mode, interrupts on crests and troughs of counter

          values and triggers to start conversion by the A/D converter can be

          skipped.

          skipped

    - Interrupt sources: 43 sources.

    - Buffer operation:

        - Automatic transfer of register data (transfer from the buffer
@@ -68,9 +68,9 @@ description: | 
        - A/D converter start triggers can be generated

        - A/D converter start request delaying function enables A/D converter

          to be started with any desired timing and to be synchronized with

          PWM output.

          PWM output

    - Low power consumption function

        - The MTU3a can be placed in the module-stop state.

        - The MTU3a can be placed in the module-stop state



    There are two phase counting modes. 16-bit phase counting mode in which

    MTU1 and MTU2 operate independently, and cascade connection 32-bit phase