Unverified Commit b1712f94 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'renesas-clk-for-v6.17-tag2' of... 

Merge tag 'renesas-clk-for-v6.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Expanded Serial Peripheral Interface (xSPI) clocks and resets on
   Renesas RZ/V2H(P) and RZ/V2N
 - Add SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
 - Add SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
 - Add Ethernet clocks and resets on Renesas RZ/G3E
 - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
  (R9A09G087) SoCs
 - Add Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
 - Add timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on
   Renesas RZ/V2N
 - Rework Module Stop and Power Domain support on the Renesas
   RZ/G2L family of SoCs (especially on RZ/G3S)
 - Add I3C clocks and resets on Renesas RZ/G3E

* tag 'renesas-clk-for-v6.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (42 commits)
  clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  clk: renesas: r9a09g057: Add XSPI clock/reset
  clk: renesas: r9a09g056: Add XSPI clock/reset
  clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
  clk: renesas: r9a09g057: Add support for xspi mux and divider
  clk: renesas: r9a09g056: Add support for xspi mux and divider
  clk: renesas: r9a09g077: Add RIIC module clocks
  clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
  clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
  clk: renesas: r9a09g057: Add entries for the RSPIs
  dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
  dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
  clk: renesas: rzv2h: Add missing include file
  clk: renesas: rzv2h: Use devm_kmemdup_array()
  clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
  clk: renesas: r9a09g077: Add PCLKL core clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
  ...
parents 19272b37 0ab2d84f

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+38 −11
Original line number Diff line number Diff line
@@ -52,9 +52,16 @@ properties: 
      - renesas,r8a779f0-cpg-mssr # R-Car S4-8

      - renesas,r8a779g0-cpg-mssr # R-Car V4H

      - renesas,r8a779h0-cpg-mssr # R-Car V4M

      - renesas,r9a09g077-cpg-mssr # RZ/T2H

      - renesas,r9a09g087-cpg-mssr # RZ/N2H



  reg:

    maxItems: 1

    minItems: 1

    items:

      - description: base address of register block 0

      - description: base address of register block 1

    description: base addresses of clock controller. Some controllers

      (like r9a09g077) use two blocks instead of a single one.



  clocks:

    minItems: 1
@@ -92,7 +99,35 @@ properties: 
      the datasheet.

    const: 1



if:



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - renesas,r9a09g077-cpg-mssr

              - renesas,r9a09g087-cpg-mssr

    then:

      properties:

        reg:

          minItems: 2

        clock-names:

          items:

            - const: extal

    else:

      properties:

        reg:

          maxItems: 1

  - if:

      not:

        properties:

          compatible:
@@ -103,14 +138,6 @@ then: 
      required:

        - '#reset-cells'



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+1 −17
Original line number Diff line number Diff line
@@ -57,8 +57,7 @@ properties: 
      can be power-managed through Module Standby should refer to the CPG device

      node in their "power-domains" property, as documented by the generic PM

      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

      The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could

      be used to reference individual CPG power domains.

    const: 0



  '#reset-cells':

    description:
@@ -77,21 +76,6 @@ required: 


additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a08g045-cpg

    then:

      properties:

        '#power-domain-cells':

          const: 1

    else:

      properties:

        '#power-domain-cells':

          const: 0



examples:

  - |

    cpg: clock-controller@11010000 {

Documentation/devicetree/bindings/soc/renesas/renesas.yaml

+10 −0
Original line number Diff line number Diff line
@@ -602,6 +602,16 @@ properties: 
              - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security

          - const: renesas,r9a09g077



      - description: RZ/N2H (R9A09G087)

        items:

          - enum:

              - renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)

          - enum:

              - renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security

              - renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security

              - renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security

          - const: renesas,r9a09g087



additionalProperties: true



...

drivers/clk/renesas/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -43,6 +43,8 @@ config CLK_RENESAS 
	select CLK_R9A09G047 if ARCH_R9A09G047

	select CLK_R9A09G056 if ARCH_R9A09G056

	select CLK_R9A09G057 if ARCH_R9A09G057

	select CLK_R9A09G077 if ARCH_R9A09G077

	select CLK_R9A09G087 if ARCH_R9A09G087

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -208,6 +210,14 @@ config CLK_R9A09G057 
       bool "RZ/V2H(P) clock support" if COMPILE_TEST

       select CLK_RZV2H



config CLK_R9A09G077

	bool "RZ/T2H clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR



config CLK_R9A09G087

	bool "RZ/N2H clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSSR



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP

drivers/clk/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o 
obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o

obj-$(CONFIG_CLK_R9A09G056)		+= r9a09g056-cpg.o

obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o

obj-$(CONFIG_CLK_R9A09G077)		+= r9a09g077-cpg.o

obj-$(CONFIG_CLK_R9A09G087)		+= r9a09g077-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family