Commit b1ca3847 authored by Ben Skeggs's avatar Ben Skeggs Committed by Dave Airlie
Browse files

drm/nouveau/gv100-: switch to volta semaphore methods 



HOPPER_CHANNEL_GPFIFO_A removes the SEMAPHORE[A-D] methods that are
currently used by nouveau to implement fences on GF100 and newer.

Switch to the newer SEM methods available from VOLTA_CHANNEL_GPFIFO,
which are also available on the Hopper/Blackwell host classes.

Signed-off-by: default avatarBen Skeggs <bskeggs@nvidia.com>
Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
Reviewed-by: default avatarTimur Tabi <ttabi@nvidia.com>
Tested-by: default avatarTimur Tabi <ttabi@nvidia.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 6c3ac7bc

drivers/gpu/drm/nouveau/Kbuild

+1 −0
Original line number Diff line number Diff line
@@ -69,5 +69,6 @@ nouveau-y += nv17_fence.o 
nouveau-y += nv50_fence.o

nouveau-y += nv84_fence.o

nouveau-y += nvc0_fence.o

nouveau-y += gv100_fence.o



obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o

drivers/gpu/drm/nouveau/gv100_fence.c

0 → 100644
+93 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT

 *

 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.

 */

#include "nouveau_drv.h"

#include "nouveau_dma.h"

#include "nouveau_fence.h"



#include "nv50_display.h"



#include <nvif/push906f.h>



#include <nvhw/class/clc36f.h>



static int

gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)

{

	struct nvif_push *push = &chan->chan.push;

	int ret;



	ret = PUSH_WAIT(push, 8);

	if (ret)

		return ret;



	PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),

				SEM_ADDR_HI, upper_32_bits(virtual),

				SEM_PAYLOAD_LO, sequence);



	PUSH_MTHD(push, NVC36F, SEM_EXECUTE,

		  NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |

		  NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |

		  NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |

		  NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));



	PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);



	PUSH_KICK(push);

	return 0;

}



static int

gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)

{

	struct nvif_push *push = &chan->chan.push;

	int ret;



	ret = PUSH_WAIT(push, 6);

	if (ret)

		return ret;



	PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),

				SEM_ADDR_HI, upper_32_bits(virtual),

				SEM_PAYLOAD_LO, sequence);



	PUSH_MTHD(push, NVC36F, SEM_EXECUTE,

		  NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |

		  NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |

		  NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));



	PUSH_KICK(push);

	return 0;

}



static int

gv100_fence_context_new(struct nouveau_channel *chan)

{

	struct nv84_fence_chan *fctx;

	int ret;



	ret = nv84_fence_context_new(chan);

	if (ret)

		return ret;



	fctx = chan->fence;

	fctx->base.emit32 = gv100_fence_emit32;

	fctx->base.sync32 = gv100_fence_sync32;

	return 0;

}



int

gv100_fence_create(struct nouveau_drm *drm)

{

	struct nv84_fence_priv *priv;

	int ret;



	ret = nv84_fence_create(drm);

	if (ret)

		return ret;



	priv = drm->fence;

	priv->base.context_new = gv100_fence_context_new;

	return 0;

}

drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h

0 → 100644
+52 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT

 *

 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.

 */

#ifndef _clc36f_h_

#define _clc36f_h_



#define NVC36F_NON_STALL_INTERRUPT                                 (0x00000020)

#define NVC36F_NON_STALL_INTERRUPT_HANDLE                                 31:0

#define NVC36F_SEM_ADDR_LO                                         (0x0000005c)

#define NVC36F_SEM_ADDR_LO_OFFSET                                         31:2

#define NVC36F_SEM_ADDR_HI                                         (0x00000060)

#define NVC36F_SEM_ADDR_HI_OFFSET                                          7:0

#define NVC36F_SEM_PAYLOAD_LO                                      (0x00000064)

#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD                                     31:0

#define NVC36F_SEM_PAYLOAD_HI                                      (0x00000068)

#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD                                     31:0

#define NVC36F_SEM_EXECUTE                                         (0x0000006c)

#define NVC36F_SEM_EXECUTE_OPERATION                                       2:0

#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE                        0x00000000

#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE                        0x00000001

#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ                 0x00000002

#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ                   0x00000003

#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND                        0x00000004

#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR                        0x00000005

#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION                      0x00000006

#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG                            12:12

#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS                   0x00000000

#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN                    0x00000001

#define NVC36F_SEM_EXECUTE_RELEASE_WFI                                   20:20

#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS                          0x00000000

#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN                           0x00000001

#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE                                  24:24

#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT                       0x00000000

#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT                       0x00000001

#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP                             25:25

#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS                    0x00000000

#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN                     0x00000001

#define NVC36F_SEM_EXECUTE_REDUCTION                                     30:27

#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN                           0x00000000

#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX                           0x00000001

#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR                           0x00000002

#define NVC36F_SEM_EXECUTE_REDUCTION_IAND                           0x00000003

#define NVC36F_SEM_EXECUTE_REDUCTION_IOR                            0x00000004

#define NVC36F_SEM_EXECUTE_REDUCTION_IADD                           0x00000005

#define NVC36F_SEM_EXECUTE_REDUCTION_INC                            0x00000006

#define NVC36F_SEM_EXECUTE_REDUCTION_DEC                            0x00000007

#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT                              31:31

#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED                  0x00000000

#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED                0x00000001



#endif

drivers/gpu/drm/nouveau/include/nvif/push906f.h

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#ifndef PUSH906F_SUBC

// Host methods

#define PUSH906F_SUBC_NV906F	0

#define PUSH906F_SUBC_NVC36F	0



// Twod

#define PUSH906F_SUBC_NV902D	3

drivers/gpu/drm/nouveau/nouveau_drm.c

+3 −1
Original line number Diff line number Diff line
@@ -503,11 +503,13 @@ nouveau_accel_init(struct nouveau_drm *drm) 
		case KEPLER_CHANNEL_GPFIFO_B:

		case MAXWELL_CHANNEL_GPFIFO_A:

		case PASCAL_CHANNEL_GPFIFO_A:

			ret = nvc0_fence_create(drm);

			break;

		case VOLTA_CHANNEL_GPFIFO_A:

		case TURING_CHANNEL_GPFIFO_A:

		case AMPERE_CHANNEL_GPFIFO_A:

		case AMPERE_CHANNEL_GPFIFO_B:

			ret = nvc0_fence_create(drm);

			ret = gv100_fence_create(drm);

			break;

		default:

			break;