Commit b1de9823 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoC 



Add SoC identification for the RZ/G3L SoC using the System Controller
(SYSC) block.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260203103031.247435-5-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6de23f81

drivers/soc/renesas/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -390,6 +390,14 @@ config ARCH_R9A08G045 
	help

	  This enables support for the Renesas RZ/G3S SoC variants.



config ARCH_R9A08G046

	bool "ARM64 Platform support for R9A08G046 (RZ/G3L)"

	default y if ARCH_RENESAS

	select ARCH_RZG2L

	select SYSC_R9A08G046

	help

	  This enables support for the Renesas RZ/G3L SoC variants.



config ARCH_R9A09G011

	bool "ARM64 Platform support for R9A09G011 (RZ/V2M)"

	default y if ARCH_RENESAS
@@ -474,6 +482,10 @@ config SYSC_R9A08G045 
	bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPILE_TEST

	select SYSC_RZ



config SYSC_R9A08G046

	bool "Renesas System controller support for R9A08G046 (RZ/G3L)" if COMPILE_TEST

	select SYSC_RZ



config SYS_R9A09G047

	bool "Renesas System controller support for R9A09G047 (RZ/G3E)" if COMPILE_TEST

	select SYSC_RZ

drivers/soc/renesas/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ ifdef CONFIG_SMP 
obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o

endif

obj-$(CONFIG_SYSC_R9A08G045)	+= r9a08g045-sysc.o

obj-$(CONFIG_SYSC_R9A08G046)	+= r9a08g046-sysc.o

obj-$(CONFIG_SYS_R9A09G047)	+= r9a09g047-sys.o

obj-$(CONFIG_SYS_R9A09G056)	+= r9a09g056-sys.o

obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o

drivers/soc/renesas/r9a08g046-sysc.c

0 → 100644
+91 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * RZ/G3L System controller (SYSC) driver

 *

 * Copyright (C) 2026 Renesas Electronics Corp.

 */



#include <linux/bits.h>

#include <linux/device.h>

#include <linux/init.h>



#include "rz-sysc.h"



#define SYS_XSPI_MAP_STAADD_CS0		0x348

#define SYS_XSPI_MAP_ENDADD_CS0		0x34c

#define SYS_XSPI_MAP_STAADD_CS1		0x350

#define SYS_XSPI_MAP_ENDADD_CS1		0x354

#define SYS_GETH0_CFG			0x380

#define SYS_GETH1_CFG			0x390

#define SYS_PCIE_CFG			0x3a0

#define SYS_PCIE_MON			0x3a4

#define SYS_PCIE_PHY			0x3b4

#define SYS_I2C0_CFG			0x400

#define SYS_I2C1_CFG			0x410

#define SYS_I2C2_CFG			0x420

#define SYS_I2C3_CFG			0x430

#define SYS_I3C_CFG			0x440

#define SYS_PWRRDY_N			0xd70

#define SYS_IPCONT_SEL_CLONECH		0xe2c



static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case SYS_XSPI_MAP_STAADD_CS0:

	case SYS_XSPI_MAP_ENDADD_CS0:

	case SYS_XSPI_MAP_STAADD_CS1:

	case SYS_XSPI_MAP_ENDADD_CS1:

	case SYS_GETH0_CFG:

	case SYS_GETH1_CFG:

	case SYS_PCIE_CFG:

	case SYS_PCIE_MON:

	case SYS_PCIE_PHY:

	case SYS_I2C0_CFG:

	case SYS_I2C1_CFG:

	case SYS_I2C2_CFG:

	case SYS_I2C3_CFG:

	case SYS_I3C_CFG:

	case SYS_PWRRDY_N:

	case SYS_IPCONT_SEL_CLONECH:

		return true;

	default:

		return false;

	}

}



static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int reg)

{

	switch (reg) {

	case SYS_XSPI_MAP_STAADD_CS0:

	case SYS_XSPI_MAP_ENDADD_CS0:

	case SYS_XSPI_MAP_STAADD_CS1:

	case SYS_XSPI_MAP_ENDADD_CS1:

	case SYS_PCIE_CFG:

	case SYS_PCIE_PHY:

	case SYS_I2C0_CFG:

	case SYS_I2C1_CFG:

	case SYS_I2C2_CFG:

	case SYS_I2C3_CFG:

	case SYS_I3C_CFG:

	case SYS_PWRRDY_N:

	case SYS_IPCONT_SEL_CLONECH:

		return true;

	default:

		return false;

	}

}



static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data __initconst = {

	.family = "RZ/G3L",

	.id = 0x87d9447,

	.devid_offset = 0xa04,

	.revision_mask = GENMASK(31, 28),

	.specific_id_mask = GENMASK(27, 0),

};



const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst = {

	.soc_id_init_data = &rzg3l_sysc_soc_id_init_data,

	.readable_reg = rzg3l_regmap_readable_reg,

	.writeable_reg = rzg3l_regmap_writeable_reg,

	.max_register = 0xe2c,

};

drivers/soc/renesas/rz-sysc.c

+3 −0
Original line number Diff line number Diff line
@@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] = { 
#ifdef CONFIG_SYSC_R9A08G045

	{ .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data },

#endif

#ifdef CONFIG_SYSC_R9A08G046

	{ .compatible = "renesas,r9a08g046-sysc", .data = &rzg3l_sysc_init_data },

#endif

#ifdef CONFIG_SYS_R9A09G047

	{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data },

#endif

drivers/soc/renesas/rz-sysc.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ struct rz_sysc_init_data { 
};



extern const struct rz_sysc_init_data rzg3e_sys_init_data;

extern const struct rz_sysc_init_data rzg3l_sysc_init_data;

extern const struct rz_sysc_init_data rzg3s_sysc_init_data;

extern const struct rz_sysc_init_data rzv2h_sys_init_data;

extern const struct rz_sysc_init_data rzv2n_sys_init_data;