Commit b1fd28da authored by Georgi Djakov's avatar Georgi Djakov
Browse files

Merge branch 'icc-sar2130p' into icc-next 

Add driver for the network of connects present on the SAR2130P platform.

* icc-sar2130p
  dt-bindings: interconnect: qcom: document SAR2130P NoC
  interconnect: qcom: add support for SAR2130P

Link: https://lore.kernel.org/r/20241018-sar2130p-icc-v2-0-c58c73dcd19d@linaro.org


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parents 55aac0ea 92c366a5

Documentation/devicetree/bindings/interconnect/qcom,sar2130p-rpmh.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P



maintainers:

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

  - Georgi Djakov <djakov@kernel.org>



description: |

  RPMh interconnect providers support system bandwidth requirements through

  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is

  able to communicate with the BCM through the Resource State Coordinator (RSC)

  associated with each execution environment. Provider nodes must point to at

  least one RPMh device child node pertaining to their RSC and each provider

  can map to multiple RPMh resources.



  See also:: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h



properties:

  compatible:

    enum:

      - qcom,sar2130p-clk-virt

      - qcom,sar2130p-config-noc

      - qcom,sar2130p-gem-noc

      - qcom,sar2130p-lpass-ag-noc

      - qcom,sar2130p-mc-virt

      - qcom,sar2130p-mmss-noc

      - qcom,sar2130p-nsp-noc

      - qcom,sar2130p-pcie-anoc

      - qcom,sar2130p-system-noc



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 2



required:

  - compatible



allOf:

  - $ref: qcom,rpmh-common.yaml#

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sar2130p-clk-virt

              - qcom,sar2130p-mc-virt

    then:

      properties:

        reg: false

    else:

      required:

        - reg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sar2130p-pcie-anoc

    then:

      properties:

        clocks:

          items:

            - description: aggre-NOC PCIe AXI clock

            - description: cfg-NOC PCIe a-NOC AHB clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sar2130p-system-noc

    then:

      properties:

        clocks:

          items:

            - description: aggre USB3 PRIM AXI clock



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sar2130p-system-noc

              - qcom,sar2130p-pcie-anoc

    then:

      required:

        - clocks

    else:

      properties:

        clocks: false



unevaluatedProperties: false



examples:

  - |

    clk_virt: interconnect-0 {

      compatible = "qcom,sar2130p-clk-virt";

      #interconnect-cells = <2>;

      qcom,bcm-voters = <&apps_bcm_voter>;

    };



    aggre1_noc: interconnect@1680000 {

      compatible = "qcom,sar2130p-system-noc";

      reg = <0x01680000 0x29080>;

      #interconnect-cells = <2>;

      clocks = <&gcc_prim_axi_clk>;

      qcom,bcm-voters = <&apps_bcm_voter>;

    };

drivers/interconnect/qcom/Kconfig

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@@ -157,6 +157,15 @@ config INTERCONNECT_QCOM_SA8775P 
	  This is a driver for the Qualcomm Network-on-Chip on sa8775p-based

	  platforms.



config INTERCONNECT_QCOM_SAR2130P

	tristate "Qualcomm SAR2130P interconnect driver"

	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

	select INTERCONNECT_QCOM_RPMH

	select INTERCONNECT_QCOM_BCM_VOTER

	help

	  This is a driver for the Qualcomm Network-on-Chip on SAR2130P-based

	  platforms.



config INTERCONNECT_QCOM_SC7180

	tristate "Qualcomm SC7180 interconnect driver"

	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

drivers/interconnect/qcom/Makefile

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@@ -20,6 +20,7 @@ qnoc-qcs8300-objs := qcs8300.o 
qnoc-qdu1000-objs			:= qdu1000.o

icc-rpmh-obj				:= icc-rpmh.o

qnoc-sa8775p-objs			:= sa8775p.o

qnoc-sar2130p-objs			:= sar2130p.o

qnoc-sc7180-objs			:= sc7180.o

qnoc-sc7280-objs                        := sc7280.o

qnoc-sc8180x-objs			:= sc8180x.o
@@ -59,6 +60,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_QCS8300) += qnoc-qcs8300.o 
obj-$(CONFIG_INTERCONNECT_QCOM_QDU1000) += qnoc-qdu1000.o

obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o

obj-$(CONFIG_INTERCONNECT_QCOM_SA8775P) += qnoc-sa8775p.o

obj-$(CONFIG_INTERCONNECT_QCOM_SAR2130P) += qnoc-sar2130p.o

obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o

obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o

obj-$(CONFIG_INTERCONNECT_QCOM_SC8180X) += qnoc-sc8180x.o

drivers/interconnect/qcom/sar2130p.c

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include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2024, Linaro Ltd.

 */



#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H

#define __DT_BINDINGS_INTERCONNECT_QCOM_SAR2130P_H



#define MASTER_QUP_CORE_0			0

#define MASTER_QUP_CORE_1			1

#define SLAVE_QUP_CORE_0			2

#define SLAVE_QUP_CORE_1			3



#define MASTER_GEM_NOC_CNOC			0

#define MASTER_GEM_NOC_PCIE_SNOC		1

#define MASTER_QDSS_DAP				2

#define SLAVE_AHB2PHY_SOUTH			3

#define SLAVE_AOSS				4

#define SLAVE_CAMERA_CFG			5

#define SLAVE_CLK_CTL				6

#define SLAVE_CDSP_CFG				7

#define SLAVE_RBCPR_CX_CFG			8

#define SLAVE_RBCPR_MMCX_CFG			9

#define SLAVE_RBCPR_MXA_CFG			10

#define SLAVE_RBCPR_MXC_CFG			11

#define SLAVE_CPR_NSPCX				12

#define SLAVE_CRYPTO_0_CFG			13

#define SLAVE_CX_RDPM				14

#define SLAVE_DISPLAY_CFG			15

#define SLAVE_GFX3D_CFG				16

#define SLAVE_IMEM_CFG				17

#define SLAVE_IPC_ROUTER_CFG			18

#define SLAVE_LPASS				19

#define SLAVE_MX_RDPM				20

#define SLAVE_PCIE_0_CFG			21

#define SLAVE_PCIE_1_CFG			22

#define SLAVE_PDM				23

#define SLAVE_PIMEM_CFG				24

#define SLAVE_PRNG				25

#define SLAVE_QDSS_CFG				26

#define SLAVE_QSPI_0				27

#define SLAVE_QUP_0				28

#define SLAVE_QUP_1				29

#define SLAVE_SDCC_1				30

#define SLAVE_TCSR				31

#define SLAVE_TLMM				32

#define SLAVE_TME_CFG				33

#define SLAVE_USB3_0				34

#define SLAVE_VENUS_CFG				35

#define SLAVE_VSENSE_CTRL_CFG			36

#define SLAVE_WLAN_Q6_CFG			37

#define SLAVE_DDRSS_CFG				38

#define SLAVE_CNOC_MNOC_CFG			39

#define SLAVE_SNOC_CFG				40

#define SLAVE_IMEM				41

#define SLAVE_PIMEM				42

#define SLAVE_SERVICE_CNOC			43

#define SLAVE_PCIE_0				44

#define SLAVE_PCIE_1				45

#define SLAVE_QDSS_STM				46

#define SLAVE_TCU				47



#define MASTER_GPU_TCU				0

#define MASTER_SYS_TCU				1

#define MASTER_APPSS_PROC			2

#define MASTER_GFX3D				3

#define MASTER_MNOC_HF_MEM_NOC			4

#define MASTER_MNOC_SF_MEM_NOC			5

#define MASTER_COMPUTE_NOC			6

#define MASTER_ANOC_PCIE_GEM_NOC		7

#define MASTER_SNOC_GC_MEM_NOC			8

#define MASTER_SNOC_SF_MEM_NOC			9

#define MASTER_WLAN_Q6				10

#define SLAVE_GEM_NOC_CNOC			11

#define SLAVE_LLCC				12

#define SLAVE_MEM_NOC_PCIE_SNOC			13



#define MASTER_CNOC_LPASS_AG_NOC		0

#define MASTER_LPASS_PROC			1

#define SLAVE_LPASS_CORE_CFG			2

#define SLAVE_LPASS_LPI_CFG			3

#define SLAVE_LPASS_MPU_CFG			4

#define SLAVE_LPASS_TOP_CFG			5

#define SLAVE_LPASS_SNOC			6

#define SLAVE_SERVICES_LPASS_AML_NOC		7

#define SLAVE_SERVICE_LPASS_AG_NOC		8



#define MASTER_LLCC				0

#define SLAVE_EBI1				1



#define MASTER_CAMNOC_HF			0

#define MASTER_CAMNOC_ICP			1

#define MASTER_CAMNOC_SF			2

#define MASTER_LSR				3

#define MASTER_MDP				4

#define MASTER_CNOC_MNOC_CFG			5

#define MASTER_VIDEO				6

#define MASTER_VIDEO_CV_PROC			7

#define MASTER_VIDEO_PROC			8

#define MASTER_VIDEO_V_PROC			9

#define SLAVE_MNOC_HF_MEM_NOC			10

#define SLAVE_MNOC_SF_MEM_NOC			11

#define SLAVE_SERVICE_MNOC			12



#define MASTER_CDSP_NOC_CFG			0

#define MASTER_CDSP_PROC			1

#define SLAVE_CDSP_MEM_NOC			2

#define SLAVE_SERVICE_NSP_NOC			3



#define MASTER_PCIE_0				0

#define MASTER_PCIE_1				1

#define SLAVE_ANOC_PCIE_GEM_NOC			2



#define MASTER_GIC_AHB				0

#define MASTER_QDSS_BAM				1

#define MASTER_QSPI_0				2

#define MASTER_QUP_0				3

#define MASTER_QUP_1				4

#define MASTER_A2NOC_SNOC			5

#define MASTER_CNOC_DATAPATH			6

#define MASTER_LPASS_ANOC			7

#define MASTER_SNOC_CFG				8

#define MASTER_CRYPTO				9

#define MASTER_PIMEM				10

#define MASTER_GIC				11

#define MASTER_QDSS_ETR				12

#define MASTER_QDSS_ETR_1			13

#define MASTER_SDCC_1				14

#define MASTER_USB3_0				15

#define SLAVE_A2NOC_SNOC			16

#define SLAVE_SNOC_GEM_NOC_GC			17

#define SLAVE_SNOC_GEM_NOC_SF			18

#define SLAVE_SERVICE_SNOC			19



#endif