Commit b2194a4c authored by Ciprian Marian Costea's avatar Ciprian Marian Costea Committed by Shawn Guo
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arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3



Add I2C[0..2] for S32G2 and S32G3 SoCs.

Signed-off-by: default avatarCiprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Reviewed-by: default avatarMatthias Brugger <mbrugger@suse.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent dc5fb736
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+55 −0
Original line number Diff line number Diff line
@@ -333,6 +333,39 @@ uart1: serial@401cc000 {
			status = "disabled";
		};

		i2c0: i2c@401e4000 {
			compatible = "nxp,s32g2-i2c";
			reg = <0x401e4000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c1: i2c@401e8000 {
			compatible = "nxp,s32g2-i2c";
			reg = <0x401e8000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c2: i2c@401ec000 {
			compatible = "nxp,s32g2-i2c";
			reg = <0x401ec000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
@@ -341,6 +374,28 @@ uart2: serial@402bc000 {
			status = "disabled";
		};

		i2c3: i2c@402d8000 {
			compatible = "nxp,s32g2-i2c";
			reg = <0x402d8000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c4: i2c@402dc000 {
			compatible = "nxp,s32g2-i2c";
			reg = <0x402dc000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		usdhc0: mmc@402f0000 {
			compatible = "nxp,s32g2-usdhc";
			reg = <0x402f0000 0x1000>;
+60 −0
Original line number Diff line number Diff line
@@ -390,6 +390,42 @@ uart1: serial@401cc000 {
			status = "disabled";
		};

		i2c0: i2c@401e4000 {
			compatible = "nxp,s32g3-i2c",
				     "nxp,s32g2-i2c";
			reg = <0x401e4000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c1: i2c@401e8000 {
			compatible = "nxp,s32g3-i2c",
				     "nxp,s32g2-i2c";
			reg = <0x401e8000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c2: i2c@401ec000 {
			compatible = "nxp,s32g3-i2c",
				     "nxp,s32g2-i2c";
			reg = <0x401ec000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g3-linflexuart",
				     "fsl,s32v234-linflexuart";
@@ -398,6 +434,30 @@ uart2: serial@402bc000 {
			status = "disabled";
		};

		i2c3: i2c@402d8000 {
			compatible = "nxp,s32g3-i2c",
				     "nxp,s32g2-i2c";
			reg = <0x402d8000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		i2c4: i2c@402dc000 {
			compatible = "nxp,s32g3-i2c",
				     "nxp,s32g2-i2c";
			reg = <0x402dc000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 40>;
			clock-names = "ipg";
			status = "disabled";
		};

		usdhc0: mmc@402f0000 {
			compatible = "nxp,s32g3-usdhc",
				     "nxp,s32g2-usdhc";