Commit b246caa6 authored by Wayne Chang's avatar Wayne Chang Committed by Vinod Koul
Browse files

phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7 



The USB2 Bias Pad Control register manages analog parameters for signal
detection. Previously, the HS_DISCON_LEVEL relied on hardware reset
values, which may lead to the detection failure.

Explicitly configure HS_DISCON_LEVEL to 0x7. This ensures the disconnect
threshold is sufficient to guarantee reliable detection.

Fixes: bbf71168 ("phy: tegra: xusb: Add Tegra186 support")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarWayne Chang <waynec@nvidia.com>
Link: https://patch.msgid.link/20251212032116.768307-1-waynec@nvidia.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 7d8f725b

drivers/phy/tegra/xusb-tegra186.c

+3 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ 
#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284

#define  BIAS_PAD_PD				BIT(11)

#define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)

#define  HS_DISCON_LEVEL(x)			(((x) & 0x7) << 3)



#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288

#define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
@@ -623,6 +624,8 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) 
	value &= ~BIAS_PAD_PD;

	value &= ~HS_SQUELCH_LEVEL(~0);

	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);

	value &= ~HS_DISCON_LEVEL(~0);

	value |= HS_DISCON_LEVEL(0x7);

	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);



	udelay(1);