Commit b299ea00 authored by Heiner Kallweit's avatar Heiner Kallweit Committed by Jakub Kicinski
Browse files

r8169: adjust version numbering for RTL8126 



Adjust version numbering for RTL8126, so that it doesn't overlap with
new RTL8125 versions.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Link: https://patch.msgid.link/6a354364-20e9-48ad-a198-468264288757@gmail.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 9163b05e

drivers/net/ethernet/realtek/r8169.h

+2 −2
Original line number Diff line number Diff line
@@ -69,8 +69,8 @@ enum mac_version { 
	RTL_GIGA_MAC_VER_61,

	RTL_GIGA_MAC_VER_63,

	RTL_GIGA_MAC_VER_64,

	RTL_GIGA_MAC_VER_65,

	RTL_GIGA_MAC_VER_66,

	RTL_GIGA_MAC_VER_70,

	RTL_GIGA_MAC_VER_71,

	RTL_GIGA_MAC_NONE

};

drivers/net/ethernet/realtek/r8169_main.c

+31 −31
Original line number Diff line number Diff line
@@ -140,8 +140,8 @@ static const struct { 
	/* reserve 62 for CFG_METHOD_4 in the vendor driver */

	[RTL_GIGA_MAC_VER_63] = {"RTL8125B",		FIRMWARE_8125B_2},

	[RTL_GIGA_MAC_VER_64] = {"RTL8125D",		FIRMWARE_8125D_1},

	[RTL_GIGA_MAC_VER_65] = {"RTL8126A",		FIRMWARE_8126A_2},

	[RTL_GIGA_MAC_VER_66] = {"RTL8126A",		FIRMWARE_8126A_3},

	[RTL_GIGA_MAC_VER_70] = {"RTL8126A",		FIRMWARE_8126A_2},

	[RTL_GIGA_MAC_VER_71] = {"RTL8126A",		FIRMWARE_8126A_3},

};



static const struct pci_device_id rtl8169_pci_tbl[] = {
@@ -1228,7 +1228,7 @@ static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 
	case RTL_GIGA_MAC_VER_31:

		r8168dp_2_mdio_write(tp, location, val);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:

		r8168g_mdio_write(tp, location, val);

		break;

	default:
@@ -1243,7 +1243,7 @@ static int rtl_readphy(struct rtl8169_private *tp, int location) 
	case RTL_GIGA_MAC_VER_28:

	case RTL_GIGA_MAC_VER_31:

		return r8168dp_2_mdio_read(tp, location);

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:

		return r8168g_mdio_read(tp, location);

	default:

		return r8169_mdio_read(tp, location);
@@ -1574,7 +1574,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 
		break;

	case RTL_GIGA_MAC_VER_34:

	case RTL_GIGA_MAC_VER_37:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71:

		r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts);

		break;

	default:
@@ -2047,7 +2047,7 @@ static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 
		tp->tx_lpi_timer = timer_val;

		r8168_mac_ocp_write(tp, 0xe048, timer_val);

		break;

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:

		tp->tx_lpi_timer = timer_val;

		RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);

		break;
@@ -2255,8 +2255,8 @@ static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 
		enum mac_version ver;

	} mac_info[] = {

		/* 8126A family. */

		{ 0x7cf, 0x64a,	RTL_GIGA_MAC_VER_66 },

		{ 0x7cf, 0x649,	RTL_GIGA_MAC_VER_65 },

		{ 0x7cf, 0x64a,	RTL_GIGA_MAC_VER_71 },

		{ 0x7cf, 0x649,	RTL_GIGA_MAC_VER_70 },



		/* 8125D family. */

		{ 0x7cf, 0x688,	RTL_GIGA_MAC_VER_64 },
@@ -2526,7 +2526,7 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_61:

		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);

		break;

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71:

		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |

			RX_PAUSE_SLOT_ON);

		break;
@@ -2658,7 +2658,7 @@ static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);

		break;

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71:

		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);

		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
@@ -2901,7 +2901,7 @@ static void rtl_enable_exit_l1(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:

		rtl_eri_set_bits(tp, 0xd4, 0x0c00);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:

		r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);

		break;

	default:
@@ -2915,7 +2915,7 @@ static void rtl_disable_exit_l1(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:

		rtl_eri_clear_bits(tp, 0xd4, 0x1f00);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:

		r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);

		break;

	default:
@@ -2941,8 +2941,8 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 


		rtl_mod_config5(tp, 0, ASPM_en);

		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_66:

		case RTL_GIGA_MAC_VER_70:

		case RTL_GIGA_MAC_VER_71:

			val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;

			RTL_W8(tp, INT_CFG0_8125, val8);

			break;
@@ -2953,7 +2953,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 


		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:

			/* reset ephy tx/rx disable timer */

			r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);

			/* chip can trigger L1.2 */
@@ -2965,7 +2965,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 
	} else {

		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:

			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);

			break;

		default:
@@ -2973,8 +2973,8 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 
		}



		switch (tp->mac_version) {

		case RTL_GIGA_MAC_VER_65:

		case RTL_GIGA_MAC_VER_66:

		case RTL_GIGA_MAC_VER_70:

		case RTL_GIGA_MAC_VER_71:

			val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;

			RTL_W8(tp, INT_CFG0_8125, val8);

			break;
@@ -3694,12 +3694,12 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 
	/* disable new tx descriptor format */

	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);



	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_71)

		RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);



	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_71)

		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);

	else if (tp->mac_version == RTL_GIGA_MAC_VER_63)

		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
@@ -3717,8 +3717,8 @@ static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 
	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);

	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);

	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);

	if (tp->mac_version == RTL_GIGA_MAC_VER_65 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_66)

	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_71)

		r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);

	else

		r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
@@ -3837,8 +3837,8 @@ static void rtl_hw_config(struct rtl8169_private *tp) 
		[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,

		[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,

		[RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,

		[RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a,

		[RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a,

		[RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,

		[RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a,

	};



	if (hw_configs[tp->mac_version])
@@ -3859,8 +3859,8 @@ static void rtl_hw_start_8125(struct rtl8169_private *tp) 
			RTL_W32(tp, i, 0);

		break;

	case RTL_GIGA_MAC_VER_63:

	case RTL_GIGA_MAC_VER_65:

	case RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_70:

	case RTL_GIGA_MAC_VER_71:

		for (i = 0xa00; i < 0xa80; i += 4)

			RTL_W32(tp, i, 0);

		RTL_W16(tp, INT_CFG1_8125, 0x0000);
@@ -4092,7 +4092,7 @@ static void rtl8169_cleanup(struct rtl8169_private *tp) 
		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);

		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);

		break;

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:

		rtl_enable_rxdvgate(tp);

		fsleep(2000);

		break;
@@ -4249,7 +4249,7 @@ static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 


	switch (tp->mac_version) {

	case RTL_GIGA_MAC_VER_34:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:

		padto = max_t(unsigned int, padto, ETH_ZLEN);

		break;

	default:
@@ -5267,7 +5267,7 @@ static void rtl_hw_initialize(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:

		rtl_hw_init_8168g(tp);

		break;

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66:

	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:

		rtl_hw_init_8125(tp);

		break;

	default:

drivers/net/ethernet/realtek/r8169_phy_config.c

+2 −2
Original line number Diff line number Diff line
@@ -1162,8 +1162,8 @@ void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 
		[RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,

		[RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,

		[RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,

		[RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,

		[RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,

		[RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config,

		[RTL_GIGA_MAC_VER_71] = rtl8126a_hw_phy_config,

	};



	if (phy_configs[ver])